US5159573A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for controlling outputs of read data in a semiconductor memory device
Assignee: NEC Electronics Corp
•
Filing: 1990-11-09
•
Granted: 1992-10-27
•
Expires: 2010-11-09
Abstract
Abstract An apparatus for controlling outputs of read data in a semiconductor memory device, includes a plurality of output circuits, through which read data are supplied to an external circuit, an output controlling circuit which controls output operation of the output circuits, an address change detecting circuit which supplies an address detecting signal to the output controlling circuit, and a timing controlling circuit which controls the timing by which an output controlling signal of the output controlling circuit is supplied to the output circuits. The timing controlling circuit controls the timing of discharge in the output terminals of the output circuits, so that the discharge occurs in the output circuits sequentially with a predetermined time interval. Consequently, noise which affects the output circuits' ability to receive read data is prevented during discharge.
Inventors
- 👤 Yasumasa Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:12
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
226 words
An apparatus for controlling outputs of read data in a semiconductor memory device, comprising: a plurality of output circuits for supplying read data which are read from a memory to an external circuit, said plurality of output circuits being provided in parallel to carry out parallel outputs of said read data; and control means for controlling said plurality of output circuits to carry out discharge of charge accumulated in said plurality of output circuits sequentially with a predetermined time difference by control signals generated in accordance with said predetermined time difference, said charges being accumulated by read data of a high level supplied to said plurality of output circuits prior to said discharge, said control means including a plurality of timing circuits for providing the control signals with said predetermined time difference, said timing circuits corresponding to said output circuits and erasing states stored in said output circuits prior to said discharge, said timing circuits are AND circuits which are connected in serial, such that an output of each AND circuit excluding a final stage-AND circuit is connected to an input of a following stage-AND circuit, each output of said AND circuits being connected to a corresponding one of said output circuits, and a signal requesting a supply of said read data to said external circuit being applied to two inputs of a first stage-AND circuit.
Claim 2
Independent Claim
226 words
An apparatus for controlling outputs of read data in a semiconductor memory device, comprising: a plurality of output circuits for supplying read data which are read from a memory to an external circuit, said plurality of output circuits being provided in parallel to carry out parallel outputs of said read data; and control means for controlling said plurality of output circuits to carry out discharge of charge accumulated in said plurality of output circuits sequentially with a predetermined time difference by control signals generated in accordance with said predetermined time difference, said charges being accumulated by read data of a high level supplied to said plurality of output circuits prior to said discharge, said control means including a plurality of timing circuits for providing the control signals with said predetermined time difference, said timing circuits corresponding to said output circuits and erasing states stored in said output circuits prior to said discharge, said timing circuits are AND circuits which are connected in serial, such that an output of each AND circuit excluding a final stage-AND circuit is connected to an input of a following stage-AND circuit, each output of said AND circuits being connected to a corresponding one of said output circuits, and a signal requesting a supply of said read data to said external circuit being applied to two inputs of a first stage-AND circuit.
Claim 3
Dependent Claim
58 words
An apparatus for controlling outputs of read data in a semiconductor memory device, according to claim 1, further comprising: request signal supply means for producing a request signal requesting a supply of said read data to said external circuit, said request signal being supplied to said control means to carry out a time-sequential supply of said read data.
Claim 4
Dependent Claim
39 words
An apparatus for controlling outputs of read data in a semiconductor memory device, according to claim 2, wherein: said request signal supply means produces said request signal by receiving a chip selecting signal and a memory address change signal.
Claim 5
Dependent Claim
50 words
An apparatus for controlling outputs of read data in a semiconductor memory device, according to claim 2, further comprising: means for detecting a change of a memory address to produce a memory address change signal which is supplied to said request signal supply means along with a chip selecting signal.
References Cited (Backward Citations)
US4672587A
Cited
US4858188A
Cited
US4894803A
Cited
US4891793A
Cited
US4928265A
Cited
US4903240A
Cited
US4908796A
Cited
US5025422A
Cited
US4972374A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |