Registered outputs for a memory device

Claim 3

The method set forth in claim 1, wherein said step of enabling an output driver circuit occurs at a predetermined time delay after said first transition.

Claim 4

Apparatus for providing data at an output terminal of a memory device comprising: (a) means for storing data from a sense amplifier in said memory device upon a first transition of an output enable signal externally applied to said memory device; (b) means for receiving a chip enable signal provided externally to said memory device, upon a second transition, opposite to said first transition, of said output enable signal, and placing a first logic level on an internal node of said memory device if said chip enable signal is within a predetermined voltage range; and (c) means for enabling an output driver circuit, coupled to said means for storing data, drive said output terminal of said memory device in response to data stored in said means for storing if said internal node is at said first logic level.

Claim 5

Apparatus for providing data at an output terminal of a memory device comprising: (a) means for storing data from a sense amplifier in said memory device upon a first transition of an output enable signal externally applied to said memory device; (b) means for receiving a chip enable signal provided externally to said memory device, upon a second transition, opposite to said first transition, of said output enable signal, and placing a first logic level on an internal node of said memory device if said chip enable signal is within a predetermined voltage range; and (c) means for enabling an output driver circuit, coupled to said means for storing data, drive said output terminal of said memory device in response to data stored in said means for storing if said internal node is at said first logic level.

Claim 6

An integrated circuit memory, comprising: terminals and at least one data terminal address; at least two but no more than three terminals for incoming control signals, including an output enable signal terminal and a chip-enable signal connection; an array of memory cells; address decoding logic, connected to decode incoming address signals which may be received at said address connections and to access a selected one of said memory cells accordingly; at least one sense amplifier, connected to amplify signals which may be read out from an accessed one of said cells; and an output driver circuit, operatively connected to amplify the data output of said sense amplifier, and to drive a data output, on at least one of said data connections, accordingly; wherein, during a read operation, when said output enable signal transitions from a second state to a first state, said output driver circuit; ceases to drive said data output, and also stores an instantaneous data state in accordance with the instantaneous output of said sense amplifier, and also stores the instantaneous state of said chip-enable signal; and, when said output enable signal transitions from said first state to said second state, said output driver circuit; drives said data output in accordance with said stored instantaneous data state, but only if said stored instantaneous state of said chip-enable signal corresponds to a predetermined state.

Claim 7

An integrated circuit memory, comprising: terminals and at least one data terminal address; at least two but no more than three terminals for incoming control signals, including an output enable signal terminal and a chip-enable signal connection; an array of memory cells; address decoding logic, connected to decode incoming address signals which may be received at said address connections and to access a selected one of said memory cells accordingly; at least one sense amplifier, connected to amplify signals which may be read out from an accessed one of said cells; and an output driver circuit, operatively connected to amplify the data output of said sense amplifier, and to drive a data output, on at least one of said data connections, accordingly; wherein, during a read operation, when said output enable signal transitions from a second state to a first state, said output driver circuit; ceases to drive said data output, and also stores an instantaneous data state in accordance with the instantaneous output of said sense amplifier, and also stores the instantaneous state of said chip-enable signal; and, when said output enable signal transitions from said first state to said second state, said output driver circuit; drives said data output in accordance with said stored instantaneous data state, but only if said stored instantaneous state of said chip-enable signal corresponds to a predetermined state.

Claim 8

The memory set forth in claim 4, wherein said memory has exactly three of said connections for incoming control signals.

Claim 9

The memory set forth in claim 4, wherein said memory has exactly three of said connections for incoming control signals, consisting of said output enable connection, a write-enable signal connection, and said chip-enable signal connection.

Claim 10

The memory of claim 4, wherein said output driver circuit includes a buffer stage which is connected to respond to transitions of said output enable signal to said second state with a first delay, and to respond to transitions of said output enable signal to said first state with a second delay which is different from said first delay.

Claim 11

The memory of claim 4, wherein said output driver circuit includes a latch which is connected to receive an input corresponding to said data output of said sense amplifier.

Claim 12

The memory of claim 4, wherein said output driver circuit includes: a first D latch, which is connected to receive an input corresponding to said data output of said sense amplifier and which is clocked by a signal corresponding to said output enable signal; and a second D latch, which is connected to receive an input corresponding to said chip enable signal and which is clocked by a signal corresponding to said output enable signal.

Claim 13

The memory set forth in claim 4, wherein said output driver circuit drives said data output only after a predetermined time delay has elapsed after said transition to said second state.

Claim 14

The memory set forth in claim 10, wherein said output driver circuit ceases to drive said data output before said predetermined time delay has elapsed after said transition to said first state.