US4703457A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Register circuit used to load, hold, and dump digital logic signals
Assignee: HP Inc
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Filing: 1986-04-21
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Granted: 1987-10-27
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Expires: 2006-04-21
Abstract
Abstract A register sub-circuit for a logic system is described which is capable of loading a logic signal from a bus, holding the state of the logic signal, and dumping the logic signal onto a precharged high capacitance bus. The circuit is master/slave in operation permitting the register to simultaneously dump the current contents of the register at the same time a new value is being loaded into the register. The circuit operates with a single phase clock. The circuit is easily integratable. The circuit comprises a storage sub-circuit and one or more dump sub-circuits. The circuit presents a low capacitance load to the dump control line.
Inventors
- 👤 Paul R. Bodenstab
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
189 words
A circuit for storing the logic state of a data signal, responsive to a load signal and a clock signal and generating first and second output signals, each signal having a first and second voltage level, the circuit comprising: first switching means responsive to the load signal for connecting the data signal to a first storage node having a first and second voltage level; second switching means responsive to the clock signal for connecting the first storage node to a second storage node having a first and second voltage level; a first NOR gate having an output connected to the first output signal and having first and second inputs connected to the second storage node and the clock signal; a second NOR gate having an output connected to the second output signal and having first and second inputs connected to the clock signal and the first output signal; third switching means responsive to the second output signal for setting the first storage node to the first voltage level; and fourth switching means responsive to the first output signal for setting the first storage node to the second voltage level.
Claim 2
Dependent Claim
189 words
A circuit for storing the logic state of a data signal, responsive to a load signal and a clock signal and generating first and second output signals, each signal having a first and second voltage level, the circuit comprising: first switching means responsive to the load signal for connecting the data signal to a first storage node having a first and second voltage level; second switching means responsive to the clock signal for connecting the first storage node to a second storage node having a first and second voltage level; a first NOR gate having an output connected to the first output signal and having first and second inputs connected to the second storage node and the clock signal; a second NOR gate having an output connected to the second output signal and having first and second inputs connected to the clock signal and the first output signal; third switching means responsive to the second output signal for setting the first storage node to the first voltage level; and fourth switching means responsive to the first output signal for setting the first storage node to the second voltage level.
Claim 3
Dependent Claim
28 words
A circuit as in claim 1 further comprising: fifth switching means responsive to the first output signal for setting the second storage node to the second voltage level.
Claim 4
Dependent Claim
159 words
A circuit for transferring first and second input signals to a precharged output bus responsive to a dump signal and a clock signal, the output bus and each signal having a first and second voltage level, the circuit comprising: first switching means responsive to the second input signal for setting a first storage node to the second voltage level; second switching means responsive to the second input signal for setting a second storage node to the second voltage level; third switching means responsive to the first input signal for connecting the first storage node to the dump signal; fourth switching means responsive to the first input signal for setting the second storage node to the second voltage level; fifth switching means responsive to the first storage node for connecting the clock signal to the second storage node; and a sixth switching means responsive to the second storage node for discharging the precharged output bus to the second voltage level.
Claim 5
Dependent Claim
159 words
A circuit for transferring first and second input signals to a precharged output bus responsive to a dump signal and a clock signal, the output bus and each signal having a first and second voltage level, the circuit comprising: first switching means responsive to the second input signal for setting a first storage node to the second voltage level; second switching means responsive to the second input signal for setting a second storage node to the second voltage level; third switching means responsive to the first input signal for connecting the first storage node to the dump signal; fourth switching means responsive to the first input signal for setting the second storage node to the second voltage level; fifth switching means responsive to the first storage node for connecting the clock signal to the second storage node; and a sixth switching means responsive to the second storage node for discharging the precharged output bus to the second voltage level.
Claim 6
Dependent Claim
351 words
A circuit for storing the logic state of a data signal responsive to a load signal and a clock signal and for transferring the stored logic state of the data signal to a precharged output bus responsive to a dump signal and the clock signal, the output bus, data, load, clock and dump signals each having a first and second voltage level, the circuit comprising: first switching means responsive to the load signal for connecting the data signal to a first storage node having a first and second voltage level; second switching means responsive to the clock signal for connecting the first storage node to a second storage node having a first and second voltage level; a first NOR gate having an output signal and having first and second inputs connected to the second storage node and the clock signal; a second NOR gate having an output signal and having first and second inputs connected to the clock signal and the output signal of the first NOR gate; third switching means responsive to the output signal of the second NOR gate for setting the first storage node to the first voltage level; fourth switching means responsive to the output signal of the first NOR gate for setting the first storage node to the second voltage level; fifth switching means responsive to the output signal of the second NOR gate for setting a third storage node to the second voltage level; sixth switching means responsive to the output signal of the second NOR gate for setting a fourth storage node to the second voltage level; seventh switching means responsive to the output signal of the first NOR gate for connecting the third storage node to the dump signal; eighth switching means responsive to the output signal of the first NOR gate for setting the fourth storage node to the second voltage level; ninth switching means responsive to the third storage node for connecting the clock signal to the fourth storage node; and tenth switching means responsive to the fourth storage node for discharging the precharged output bus to the second voltage level.
Claim 7
Dependent Claim
351 words
A circuit for storing the logic state of a data signal responsive to a load signal and a clock signal and for transferring the stored logic state of the data signal to a precharged output bus responsive to a dump signal and the clock signal, the output bus, data, load, clock and dump signals each having a first and second voltage level, the circuit comprising: first switching means responsive to the load signal for connecting the data signal to a first storage node having a first and second voltage level; second switching means responsive to the clock signal for connecting the first storage node to a second storage node having a first and second voltage level; a first NOR gate having an output signal and having first and second inputs connected to the second storage node and the clock signal; a second NOR gate having an output signal and having first and second inputs connected to the clock signal and the output signal of the first NOR gate; third switching means responsive to the output signal of the second NOR gate for setting the first storage node to the first voltage level; fourth switching means responsive to the output signal of the first NOR gate for setting the first storage node to the second voltage level; fifth switching means responsive to the output signal of the second NOR gate for setting a third storage node to the second voltage level; sixth switching means responsive to the output signal of the second NOR gate for setting a fourth storage node to the second voltage level; seventh switching means responsive to the output signal of the first NOR gate for connecting the third storage node to the dump signal; eighth switching means responsive to the output signal of the first NOR gate for setting the fourth storage node to the second voltage level; ninth switching means responsive to the third storage node for connecting the clock signal to the fourth storage node; and tenth switching means responsive to the fourth storage node for discharging the precharged output bus to the second voltage level.
Claim 8
Dependent Claim
32 words
A circuit as in claim 4 further comprising: eleventh switching means responsive to the output signal of the first NOR gate for setting the second storage node to the second voltage level;
References Cited (Backward Citations)
US4570244A
Cited
US4437171A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-26 | 1991-04-27 | 1991-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-26 | 1995-04-27 | 1995-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-26 | 1999-04-27 | 1999-10-27 | $7700.00 | Window Closed / Lapsed |