ECL Compatible CMOS memory

Claim 2

In a metal-oxide-semiconductor (MOS) circuit, a buffer for receiving a signal from an emitter-coupled-logic (ECL) circuit and for converting said ECL signal to an MOS compatible signal, comprising: a comparator means for receiving said ECL signal and for comparing it with a predetermined reference potential; level shifting means, coupled to said comparator means, for shifting the signal level resulting from said comparison; amplification means for amplifying the signal shifted by said level shifter, said amplification means coupled to said level shifter; and, reference potential means integral with said MOS circuit for generating said predetermined reference potential, whereby said ECL signal is converted to an MOS compatible signal.

Claim 3

The buffer defined by claim 1 wherein said comparator means comprises a differential amplifier.

Claim 4

The buffer defined by claim 2 including biasing means for biasing said differential amplifier.

Claim 5

The buffer defined by claim 3 wherein said biasing means comprises a current mirror circuit for maintaining biasing currents in said differential amplifier.

Claim 6

The buffer defined by claim 1 wherein said amplification means includes a current mirror stage used for establishing a current in an output inverter stage.

Claim 7

The buffer defined in claim 1 wherein said level shifter includes a pair of cross-coupled transistors and means for preventing said cross-coupled transistors from becoming latched in a stable state.

Claim 8

The buffer defined by claim 1 wherein said reference potential means includes bipolar transistors.

Claim 9

In a complementary metal-oxide-semiconductor (CMOS) circuit, a buffer for receiving a signal from an emitter-coupled-logic (ECL) circuit and for converting said ECL signal to an MOS compatible signal, comprising: comparator means for receiving said ECL signal and for comparing it with a predetermined reference potential; level shifting means for shifting the level of the signal resulting from said comparison, said level shifting means coupled to said comparator means; amplification means for amplifying the output of said level shifting means, said amplification means coupled to said level shifting means; and, bipolar transistors formed integrally with said MOS circuit for providing said reference potential for said comparator means, whereby the output of said amplification means provides an MOS compatible signal.

Claim 10

In a complementary metal-oxide-semiconductor (CMOS) circuit, a buffer for receiving a signal from an emitter-coupled-logic (ECL) circuit and for converting said ECL signal to an MOS compatible signal, comprising: comparator means for receiving said ECL signal and for comparing it with a predetermined reference potential; level shifting means for shifting the level of the signal resulting from said comparison, said level shifting means coupled to said comparator means; amplification means for amplifying the output of said level shifting means, said amplification means coupled to said level shifting means; and, bipolar transistors formed integrally with said MOS circuit for providing said reference potential for said comparator means, whereby the output of said amplification means provides an MOS compatible signal.

Claim 11

The buffer defined in claim 8 wherein said comparator means includes a differential amplifier.

Claim 12

The buffer defined by claim 9 wherein a current mirror circuit is used for providing biasing for said differential amplifier.

Claim 13

The buffer defined by claim 10 wherein said level shifting means includes a pair of cross-coupled transistors and means for preventing said transistors from becoming latched.

Claim 14

The buffer defined by claim 11 wherein said amplification means includes a current mirror stage used for establishing a current in an output inverter stage.

Claim 15

In a complementary metal-oxide-semiconductor (CMOS) circuit a buffer for receiving a metal-oxide-semiconductor (MOS) level signal and for converting said MOS signal to a signal compatible with an emitter-coupled-logic (ECL) circuit, comprising: a first and a second resistor, said resistors being coupled in series; a first transistor coupled in series with said resistors; a second transistor coupled in parallel with said first resistor; said first and second transistors being field-effect transistors having their gates coupled to receive said MOS signal; and, a bipolar transistor formed integrally with said CMOS circuit, the base terminal of said bipolar transistor being coupled to said first and second resistors; whereby said bipolar transistor provides an ECL compatible signal.

Claim 16

In a complementary metal-oxide-semiconductor (CMOS) circuit a buffer for receiving a metal-oxide-semiconductor (MOS) level signal and for converting said MOS signal to a signal compatible with an emitter-coupled-logic (ECL) circuit, comprising: a first and a second resistor, said resistors being coupled in series; a first transistor coupled in series with said resistors; a second transistor coupled in parallel with said first resistor; said first and second transistors being field-effect transistors having their gates coupled to receive said MOS signal; and, a bipolar transistor formed integrally with said CMOS circuit, the base terminal of said bipolar transistor being coupled to said first and second resistors; whereby said bipolar transistor provides an ECL compatible signal.

Claim 17

The buffer defined by claim 13 wherein said first transistor comprises an n-channel transistor and said second transistor, a p-channel transistor.

Claim 18

The buffer defined by claim 14 wherein said bipolar transistor comprises an npn transistor and wherein said ECL compatible signal is obtained at the emitter terminal of said npn transistor.

Claim 19

The circuit defined by claim 13 including circuit means for preventing said ECL compatible signal from rising in potential when transitioning from its higher level to its lower level.

Claim 20

The buffer defined by claim 16 wherein said circuit means comprises: a third and fourth field-effect transistor coupled in series with said first resistor delay means for delaying said MOS signal before said MOS signal is applied to the gates of said first, second and third transistors; the gate of said fourth transistor being coupled to receive said MOS signal without said delay.

Claim 21

The buffer defined by claim 17 wherein said delayed MOS signal is the complement of said non-delayed MOS signal.