Discharge circuit for a semiconductor memory including address transition detectors

Claim 2

A semiconductor memory device comprising memory cells respectively connected to a plurality of first and second word lines, the device further comprising: address input means for receiving a row address signal required for designating selected ones of said memory cells; decoder means for decoding the row address signal from said address input means and, in response thereto, selecting one of said plurality of first word lines; transition detection means for detecting a transition of a level of the row address signal applied to said address input means and outputting a transition detection signal; and a plurality of discharge control means connected to respective ones of said plurality of first word lines and to said transition detection means, each of said discharge control means receiving the voltage of an associated first word line in response to the transition detection signal from said transition detection means; a corresponding one of said discharge control means continuing to output a discharge control signal in response to the next transition detection signal when a voltage level of a previously selected first word line of said plurality of first word lines is equal to a voltage level of said selected first word line; and switching means which continues to discharge a selected one of said second word lines in response to the discharge control signal.

Claim 3

A semiconductor memory device according to claim 1, wherein said address input means comprises address buffer means.

Claim 4

A semiconductor memory device according to claim 1, wherein said semiconductor memory device comprises a static random access memory device.

Claim 5

A semiconductor memory device according to claim 1, wherein each of said discharge control means comprises counter means responsive to the transition detection signal for counting a number of level transitions of said row address signal from said address input means.

Claim 6

A semiconductor memory device according to claim 4, wherein said counter means comprises a plurality of flip flops configured as a counter circuit.

Claim 7

A semiconductor memory device according to claim 1, wherein said switching means comprises at least one series circuit of a switching device and resistance means connected between at least one of said second word lines and a reference potential.

Claim 8

A semiconductor memory device according to claim 6, wherein said at least one series circuit comprises a first series connection of a first transistor and a first resistor, and a second series connection of a second transistor and a second resistor.

Claim 9

A semiconductor memory device comprising memory cells connected to a plurality of first and second word lines, comprising: address input means for receiving a row address signal for designating one of said memory cells; decoder means for decoding said row address signal from said address input means and selecting one of said plurality of first word lines; transition detection means for detecting a transition of a level of the row address signal applied to said address input means and outputting a transition detection signal; discharge control means connected to said transition detection means, which receives the voltage of said selected first word line for outputting a discharge control signal in response to the transition detection signal, said discharge control means including a counter responsive to said transition detection circuit and having first and second D type flip flops both connected to operate in response to the transition detection signal, ; and switching means which continues to discharge a selected one of said second word lines in response to the discharge control signal, said switching means including at least one series circuit of a switching device and resistance means connected between at least one of said second word lines and a reference potential, said at least one series circuit comprising a first series connection of a first transistor and a first resistor, and a second series connection of a second transistor and a second resistor, said first flip flop having an input connected to said selected first word line and an output connected to the input of said second flip flop and to the base of said first transistor; said second flip flop having an output connected to the base of said second transistor.

Claim 10

A semiconductor memory device comprising memory cells connected to a plurality of first and second word lines, comprising: address input means for receiving a row address signal for designating one of said memory cells; decoder means for decoding said row address signal from said address input means and selecting one of said plurality of first word lines; transition detection means for detecting a transition of a level of the row address signal applied to said address input means and outputting a transition detection signal; discharge control means connected to said transition detection means, which receives the voltage of said selected first word line for outputting a discharge control signal in response to the transition detection signal, said discharge control means including a counter responsive to said transition detection circuit and having first and second D type flip flops both connected to operate in response to the transition detection signal, ; and switching means which continues to discharge a selected one of said second word lines in response to the discharge control signal, said switching means including at least one series circuit of a switching device and resistance means connected between at least one of said second word lines and a reference potential, said at least one series circuit comprising a first series connection of a first transistor and a first resistor, and a second series connection of a second transistor and a second resistor, said first flip flop having an input connected to said selected first word line and an output connected to the input of said second flip flop and to the base of said first transistor; said second flip flop having an output connected to the base of said second transistor.

Claim 11

A semiconductor memory device comprising memory cells connected to a plurality of first and second word lines, comprising: a plurality of bit lines, each of said bit lines connected to associated ones of said memory cells, address input means for receiving a row address signal required for designating one of said memory cells, row decoder means for selecting one of said plurality of first word lines in response to the row address signal from said address input means, transition detection means connected so as to receive row address signals from said address input means, which outputs a transition detection pulse of a predetermined width in response to a transition in the row address signal from said address input means, a plurality of first control means, each of said first control means having a first input node connected to a first word line in a corresponding row, a second input connected to the output of said transition detection means, and an output node, each of said first control means receiving the potential of a corresponding first word line during a period of said predetermined pulse width in response to the transition detection pulse from said transition detection means, each of said first control means outputting at its output node a potential of a first level when the corresponding first word line is selected by said row decoder means, and a potential of a second level when the corresponding first word line is not selected by said row decoder means, until the next transition detection pulse is received, a plurality of second control means, each of said second control means having a first input node connected to the output node of a first control means in a corresponding row, a second input node connected to the output of said transition detection means, and an output node, each of said second control means outputting at its output node a potential of a first level in response to the first level from a corresponding first control means, and a potential of a second level in response to the second level from said corresponding first control means during a period of the predetermined pulse width, when a transition detection pulse is received from the transition detection means, a plurality of discharge means, each of said discharge means connected to a second word line in a corresponding row, the output node of said first control means in the corresponding row and the output node of said second control means in the corresponding row, wherein each of said discharge means discharges a corresponding second word line when a potential of a first level is received from the corresponding first control means or a potential of a first level is received from the corresponding second control means.

Claim 12

A semiconductor memory device comprising memory cells connected to a plurality of first and second word lines, comprising: a plurality of bit lines, each of said bit lines connected to associated ones of said memory cells, address input means for receiving a row address signal required for designating one of said memory cells, row decoder means for selecting one of said plurality of first word lines in response to the row address signal from said address input means, transition detection means connected so as to receive row address signals from said address input means, which outputs a transition detection pulse of a predetermined width in response to a transition in the row address signal from said address input means, a plurality of first control means, each of said first control means having a first input node connected to a first word line in a corresponding row, a second input connected to the output of said transition detection means, and an output node, each of said first control means receiving the potential of a corresponding first word line during a period of said predetermined pulse width in response to the transition detection pulse from said transition detection means, each of said first control means outputting at its output node a potential of a first level when the corresponding first word line is selected by said row decoder means, and a potential of a second level when the corresponding first word line is not selected by said row decoder means, until the next transition detection pulse is received, a plurality of second control means, each of said second control means having a first input node connected to the output node of a first control means in a corresponding row, a second input node connected to the output of said transition detection means, and an output node, each of said second control means outputting at its output node a potential of a first level in response to the first level from a corresponding first control means, and a potential of a second level in response to the second level from said corresponding first control means during a period of the predetermined pulse width, when a transition detection pulse is received from the transition detection means, a plurality of discharge means, each of said discharge means connected to a second word line in a corresponding row, the output node of said first control means in the corresponding row and the output node of said second control means in the corresponding row, wherein each of said discharge means discharges a corresponding second word line when a potential of a first level is received from the corresponding first control means or a potential of a first level is received from the corresponding second control means.