US4520462A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1982-12-14
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Granted: 1985-05-28
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Expires: 2002-12-14
Abstract
Abstract A semiconductor memory device in which a holding current continuously flows from word selection lines through memory cells to hold lines. Current mirror circuits are placed at the base of each of the transistors which switch discharge currents on and off in the word line discharge circuits. Thus, the discharge circuit is independent of the effects of the operation of other discharge circuits and the word line discharge circuit is less affected by power source fluctuations. This allows a semiconductor memory device having a high access speed.
Inventors
- 👤 Katuyuki Yamada
- 👤 Kazuhiro Toyoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
187 words
A static-type semiconductor memory device operatively connectable to a power source having a return line, in which a holding current continuously flows from word selection lines through memory cells to hold lines, said static-type semiconductor memory device comprising: a first transistor, operatively connected to one of the word selection lines, for detecting the potential charge on said one of the word selection lines and for outputting an output signal; a delay circuit, operatively connected to said first transistor, for delaying the output of said first transistor during a predetermined time and for outputting a delayed output signal; a second transistor, having a base, operatively connected to said delay circuit and disposed between one of the hold lines and the return line of the power source, said second transistor turned on and off by the delayed output signal of said delay circuit to operate as an electric current switch; a current mirror circuit operatively connected to the base of said second transistor and having an input; and a first resistor operatively connected between the input of said current mirror circuit and the return line of the power source.
Claim 2
Dependent Claim
187 words
A static-type semiconductor memory device operatively connectable to a power source having a return line, in which a holding current continuously flows from word selection lines through memory cells to hold lines, said static-type semiconductor memory device comprising: a first transistor, operatively connected to one of the word selection lines, for detecting the potential charge on said one of the word selection lines and for outputting an output signal; a delay circuit, operatively connected to said first transistor, for delaying the output of said first transistor during a predetermined time and for outputting a delayed output signal; a second transistor, having a base, operatively connected to said delay circuit and disposed between one of the hold lines and the return line of the power source, said second transistor turned on and off by the delayed output signal of said delay circuit to operate as an electric current switch; a current mirror circuit operatively connected to the base of said second transistor and having an input; and a first resistor operatively connected between the input of said current mirror circuit and the return line of the power source.
Claim 3
Dependent Claim
32 words
A semiconductor memory device as defined in claim 1, wherein said delay circuit comprises: a second resistor operatively connected to said first transistor; and a capacitor operatively connected to said second resistor.
Claim 4
Dependent Claim
27 words
A semiconductor memory device as defined in claim 2, wherein said first and second resistors are pinch resistors produced in an identical process with said second transistor.
Claim 5
Dependent Claim
20 words
A semiconductor memory device as defined in claim 1, 2, or 3, wherein said second transistor comprises Darlington connected transistors.
Claim 6
Dependent Claim
35 words
A semiconductor memory device as defined in claim 1, 2, or 3, wherein said current mirror circuit consists of a third transistor and a diode connected between the base and emitter of said third transistor.
Claim 7
Dependent Claim
44 words
A semiconductor memory device as defined in claim 4, wherein said current mirror circuit comprises: a third transistor operatively connected to said second transistor and having a base and emitter; and a diode operatively connected between the base and emitter of said third transistor.
Claim 8
Dependent Claim
82 words
A word line discharging circuit for a semiconductor memory device having word lines and hold lines and operatively connectable to a power source, comprising: a first transistor operatively connected to one of the word lines and the power source; a delay circuit operatively connected to said first transistor; a second transistor operatively connected to said delay circuit; a current mirror switch operatively connected to said second transistor; and a first resistor operatively connected between said current mirror switch and the power source.
Claim 9
Dependent Claim
82 words
A word line discharging circuit for a semiconductor memory device having word lines and hold lines and operatively connectable to a power source, comprising: a first transistor operatively connected to one of the word lines and the power source; a delay circuit operatively connected to said first transistor; a second transistor operatively connected to said delay circuit; a current mirror switch operatively connected to said second transistor; and a first resistor operatively connected between said current mirror switch and the power source.
Claim 10
Dependent Claim
48 words
A word line discharging circuit as defined in claim 7, wherein said current mirror switch comprises: a third transistor operatively connected to said second transistor; and a diode operatively connected to said third transistor forming a connection node therebetween, said first resistor operatively connected to the connection node.
Claim 11
Dependent Claim
35 words
A word line discharging circuit as defined in claim 7, wherein said delay circuit comprises: a second resistor operatively connected between said first and second transistors; and a capacitor operatively connected to said second resistor.
References Cited (Backward Citations)
JPS5341968A
Cited
US4442509A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |