US4928265A
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1988-11-02
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Granted: 1990-05-22
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Expires: 2008-11-02
Abstract
Abstract Considering the dispersion in the access time of semiconductor memories, at least a first and a second memory circuit are connected to the output of a sense amplifier. The output of the sense amplifier is an input to these two memory circuits alternatively at different timings. The data stored in these memory circuits are alternately transferred to a data output circuit. Even when the access time becomes long, the desired sense data can be successively read out from the output of the data output circuit at a short time interval determined by the clock cycle. When the access time becomes short and even when a second data is generated from the output of the sense amplifier at the timing of transferring a first data in the first memory circuit to the data output circuit, the first data held in the first memory circuit is prevented from being renewed by the second data. In this case too, the desired sense data can be successively read out from the output of the data output circuit at a time interval determined by the clock cycle.
Inventors
- 👤 Hisayuki Higuchi
- 👤 Noriyuki Homma
- 👤 Makoto Suzuki
- 👤 Suguru Tachibana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:02
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
171 words
A semiconductor integrated circuit comprising: (1) a memory matrix including a plurality of memory cells; (2) address means for selecting at least one of said plurality of memory cells of said memory matrix in response to an address signal; (3) a sense amplifier for amplifying a signal from said at least one selected memory cell; (4) a first memory circuit having an input connected to the output of said sense amplifier; (5) a second memory circuit having an input connected to the output of said sense amplifier; and (6) a signal generator for generating a first control signal and a second control signal in response to changes in said address signal, wherein the timing of said first control signal is set to be different from the timing of said second control signal, wherein said first memory circuit fetches the output of said sense amplifier in response to said first control signal, and wherein said second memory circuit fetches the output of said sense amplifier in response to said second control signal.
Claim 2
Dependent Claim
171 words
A semiconductor integrated circuit comprising: (1) a memory matrix including a plurality of memory cells; (2) address means for selecting at least one of said plurality of memory cells of said memory matrix in response to an address signal; (3) a sense amplifier for amplifying a signal from said at least one selected memory cell; (4) a first memory circuit having an input connected to the output of said sense amplifier; (5) a second memory circuit having an input connected to the output of said sense amplifier; and (6) a signal generator for generating a first control signal and a second control signal in response to changes in said address signal, wherein the timing of said first control signal is set to be different from the timing of said second control signal, wherein said first memory circuit fetches the output of said sense amplifier in response to said first control signal, and wherein said second memory circuit fetches the output of said sense amplifier in response to said second control signal.
Claim 3
Dependent Claim
88 words
A semiconductor integrated circuit according to claim 1, further comprising a data output circuit having a first and a second input connected to the output of said first memory circuit and the output of said second memory circuit, respectively, wherein said signal generator further generates a third control signal in response to changes in said address signal, and wherein said data output circuit transmits alternately the data of said first and second memory circuits to an output of the output circuit in response to said third control signal.
Claim 4
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 1, wherein said plurality of memory cells of said memory matrix are random access type memory cells.
Claim 5
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 2, wherein said plurality of memory cells of said memory matrix are static random access type memory cells.
Claim 6
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 3, wherein said plurality of memory cells of said memory matrix are dynamic random access type memory cells.
Claim 7
Dependent Claim
131 words
A semiconductor integrated circuit according to claim 2, wherein said data output circuit includes a first and a second CMOS inverter for responding to the complementary output signals of at least one of said first and second memory circuits, a first transistor having a control input terminal responding to the output of said first CMOS inverter and forming an output current path connected between a first operative potential point and the data output terminal, a second transistor having a control input terminal responding to the output of said second CMOS inverter and forming an output current path connected between said data output terminal and a second operative potential point, and current-stabilizing MOSFETs connected between said first and second CMOS inverters and said first operative potential point and allowing predetermined stabilized currents.
Claim 8
Dependent Claim
78 words
A semiconductor integrated circuit according to claim 1, further comprising: (7) an input buffer circuit for receiving said address signal, wherein said input buffer circuit includes a flip-flop circuit including a pair of first conductivity type MOSFETs responding to said address signal, and a pair of second conductivity type MOSFETs having drains connected to said pair of first conductivity type MOSFETs and gates, said gates and said drains of said pair of second conductivity type MOSFETs being crosscoupled.
Claim 9
Dependent Claim
95 words
A semiconductor integrated circuit according to claim 1, wherein said address means includes a decoder circuit including a multi-emitter transistor, a plurality of signal lines connected to the plurality of emitters of said multi-emitter transistor, and a plurality of current sources connected to said plurality of signal lines, wherein when the voltage of one of said plurality of signal lines changes from a high level to a low level, one of said plurality of current sources connected to said one signal line allows a larger current to flow than the currents of other current sources.
Claim 10
Dependent Claim
92 words
A semiconductor integrated circuit according to claim 1, wherein said address means has a decoder circuit including a multi-emitter transistor, a plurality of signal lines connected to the plurality of emitters of said multi-emitter transistor, and a plurality of current sources connected to said plurality of signal lines, and wherein when the voltage of one of said plurality of signal lines is of a low level, one of said plurality of current sources connected to said one signal line allows a larger current to flow than the currents of other current sources.
References Cited (Backward Citations)
US4773049A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-21 | 1993-11-20 | 1994-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-21 | 1997-11-20 | 1998-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-21 | 2001-11-20 | 2002-05-22 | $7700.00 | Window Closed / Lapsed |