US4773049A
Expired / Lapsed
US
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Semiconductor memory device having improved access time for continuously accessing data
Assignee: Fujitsu Ltd
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Filing: 1985-09-11
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Granted: 1988-09-20
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Expires: 2005-09-11
Abstract
Abstract The semiconductor memory device can continously read or store a plurality of data therefrom or therein. The semiconductor memory device includes a memory unit having a plurality of memory cells. The memory cells are arranged in a matrix having rows and columns. A reading/storing circuit is also provided. The reading/storing circuit can read data from or store data in the memory cell at an address corresponding to an address signal received therein in response to the first and second control signals, respectively. The reading/storing circuit also can consecutively read data from or store data in the memory cell at another address subsequent to a previous address read or stored, in response to the second control signal.
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036; G11C7/22; G11C8/00; G11C8/04; G11C8/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
460 words
A semiconductor memory device operatively connected to receive first and second control signals, comprising: memory means including first and second memory cell blocks each of which includes a plurality of memory cell, said memory cells in each of said first and second memory cell blocks being arranged in a matrix having rows and columns; first and second row selection means, operatively connected to said first and second memory cell blocks, respectively, and connected to receive a row address, for selecting one of said rows in said first and second memory cell blocks corresponding to the row address, and for selecting one of said rows alternately from one of said first and second memory cell blocks when the row address is incremented, said first and second row selection means including: means for simultaneously selecting a next one of said rows corresponding to a next row address from one of said first and second memory cell blocks while one of said rows corresponding to the received row address is selected from the other one of said first and second memory cell blocks; a plurality of data bus means, connected to said memory means, for inputting or outputting data to or from said memory means; a plurality of first and second sets of data transfer means, connected to said data bus means and to said columns of said first and second memory cell blocks, respectively, for transferring data between said data bus means and selected columns; and a plurality of column selection units, respectively, operatively connected to said first and second sets of said data transfer means, and connected to receive a column address, for designating one of said columns corresponding to the column address from one of said first and second memory cell blocks including said selection row, and selecting a predetermined number of said columns including said designated column by selecting one of said sets of said data transfer means, said selected one of said sets of data transfer means transferring data between said selected predetermined number of said columns and said data bus means, said designated column being coupled to a predetermined one of said data bus means, the remaining selected predetermined number of said columns corresponding to contiguous column addresses consecutive to the received column address, the contiguous column addresses being such that the last column address is followed by the initial column address to maintain contiguity, said column selection units selecting an initial column corresponding to the initial column address from the other one of said first and second memory cell blocks in which said next one of said rows corresponding to the next row address is included when said selected predetermined number of said columns include said initial column to maintain contiguity of the column addresses thereof.
Claim 2
Dependent Claim
460 words
A semiconductor memory device operatively connected to receive first and second control signals, comprising: memory means including first and second memory cell blocks each of which includes a plurality of memory cell, said memory cells in each of said first and second memory cell blocks being arranged in a matrix having rows and columns; first and second row selection means, operatively connected to said first and second memory cell blocks, respectively, and connected to receive a row address, for selecting one of said rows in said first and second memory cell blocks corresponding to the row address, and for selecting one of said rows alternately from one of said first and second memory cell blocks when the row address is incremented, said first and second row selection means including: means for simultaneously selecting a next one of said rows corresponding to a next row address from one of said first and second memory cell blocks while one of said rows corresponding to the received row address is selected from the other one of said first and second memory cell blocks; a plurality of data bus means, connected to said memory means, for inputting or outputting data to or from said memory means; a plurality of first and second sets of data transfer means, connected to said data bus means and to said columns of said first and second memory cell blocks, respectively, for transferring data between said data bus means and selected columns; and a plurality of column selection units, respectively, operatively connected to said first and second sets of said data transfer means, and connected to receive a column address, for designating one of said columns corresponding to the column address from one of said first and second memory cell blocks including said selection row, and selecting a predetermined number of said columns including said designated column by selecting one of said sets of said data transfer means, said selected one of said sets of data transfer means transferring data between said selected predetermined number of said columns and said data bus means, said designated column being coupled to a predetermined one of said data bus means, the remaining selected predetermined number of said columns corresponding to contiguous column addresses consecutive to the received column address, the contiguous column addresses being such that the last column address is followed by the initial column address to maintain contiguity, said column selection units selecting an initial column corresponding to the initial column address from the other one of said first and second memory cell blocks in which said next one of said rows corresponding to the next row address is included when said selected predetermined number of said columns include said initial column to maintain contiguity of the column addresses thereof.
Claim 3
Dependent Claim
45 words
A semiconductor memory device according to claim 1, wherein said first and second row selection means include: word decoders connected to said respective first and second memory cell blocks; and address increment circuits connected to receive row address signals and connected to said word decoders.
Claim 4
Dependent Claim
50 words
A semiconductor memory device according to claim 1, wherein said column selection units include: column decoder units connected to receive column address signals and a row address signal; and column selector means, connected to said column decoder units, for selecting a column decoder in accordance with the row address signal.
Claim 5
Dependent Claim
23 words
A semiconductor memory device according to claim 3, wherein said column selector means is located on either side of said column decoder units.
Claim 6
Dependent Claim
28 words
A semiconductor memory device according to claim 3, wherein said column selector means is a column transfer gate driver located on either side of said column decoder units.
Claim 7
Dependent Claim
246 words
A semiconductor memory device comprising: memory means including first and second memory cell blocks each of which includes a plurality of memory cells, said memory cells in each of said first and second memory cell blocks being arranged in a matrix having rows and columns; first and second row selection means, operatively connected to said first and second memory cell blocks, respectively, and connected to receive a row address, each of said first and second row selection means selecting one of said rows in each of said first and second memory cell blocks in dependence upon the received row address; a plurality of data bus means, coupled to said memory means, for inputting and outputting data in parallel to or from said memory means; and a plurality of sets of column selection means, coupled to said data bus means, for selecting a predetermined number of said columns having consecutive column addresses and coupling the selected columns to said data bus means for enabling data transfer therebetween, said column selection means selecting all of said selected columns from one of said first and second memory cell blocks when said consecutive column addresses are intermediate between initial and final column addresses, and selecting a part of said selected columns from one of said first and second memory cell blocks and the remaining columns from the remaining said first and second memory cell blocks when said consecutive column addresses are transitional from the final to the initial column addresses.
Claim 8
Dependent Claim
246 words
A semiconductor memory device comprising: memory means including first and second memory cell blocks each of which includes a plurality of memory cells, said memory cells in each of said first and second memory cell blocks being arranged in a matrix having rows and columns; first and second row selection means, operatively connected to said first and second memory cell blocks, respectively, and connected to receive a row address, each of said first and second row selection means selecting one of said rows in each of said first and second memory cell blocks in dependence upon the received row address; a plurality of data bus means, coupled to said memory means, for inputting and outputting data in parallel to or from said memory means; and a plurality of sets of column selection means, coupled to said data bus means, for selecting a predetermined number of said columns having consecutive column addresses and coupling the selected columns to said data bus means for enabling data transfer therebetween, said column selection means selecting all of said selected columns from one of said first and second memory cell blocks when said consecutive column addresses are intermediate between initial and final column addresses, and selecting a part of said selected columns from one of said first and second memory cell blocks and the remaining columns from the remaining said first and second memory cell blocks when said consecutive column addresses are transitional from the final to the initial column addresses.
Claim 9
Dependent Claim
45 words
A semiconductor memory device according to claim 6, wherein said first and second row selection means include: word decoders connected to said respective first and second memory cell blocks; and address increment circuits connected to receive row address signals and connected to said word decoders.
Claim 10
Dependent Claim
50 words
A semiconductors memory device according to claim 6, wherein said column selection means include: column decoder units connected to receive column address signals and a row address signal; and column selector means, connected to said column decoder units for selecting a column decoder in accordance with the row address signal.
Claim 11
Dependent Claim
22 words
A semiconductor memory device according to claim 8, wherein said column selector means is located on either side of said column decoders.
Claim 12
Dependent Claim
28 words
A semiconductor memory device according to claim 8, wherein said column selector means is a column transfer gate driver located on either side of said column decoder units.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |