US4618947A
Expired / Lapsed
US
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Dynamic memory with improved address counter for serial modes
Assignee: Texas Instruments Inc
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Filing: 1984-07-26
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Granted: 1986-10-21
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Expires: 2004-07-26
Abstract
Abstract A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.
Inventors
- 👤 Bao G. Tran
- 👤 Joseph H. Neal
- 👤 Lionel S. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
127 words
A semiconductor memory device comprising: an array of rows and columns of storage cells, row addressing means receiving a row address and activating one of said rows of cells in response thereto, column addressing means receiving a column address and selecting from said activated row a plurality of columns of cells in response to the column address, to produce column output data, and an address counter included in said column addressing means, said address counter receiving selected bits of said column address in response to a control signal to provide a stored address, the address counter including means for incrementing said stored address in response to an address control input, and means responsive to said stored address for connecting said column output data to an output terminal.
Claim 2
Dependent Claim
127 words
A semiconductor memory device comprising: an array of rows and columns of storage cells, row addressing means receiving a row address and activating one of said rows of cells in response thereto, column addressing means receiving a column address and selecting from said activated row a plurality of columns of cells in response to the column address, to produce column output data, and an address counter included in said column addressing means, said address counter receiving selected bits of said column address in response to a control signal to provide a stored address, the address counter including means for incrementing said stored address in response to an address control input, and means responsive to said stored address for connecting said column output data to an output terminal.
Claim 3
Dependent Claim
42 words
A device according to claim 1 wherein said row addressing means is responsive to said row address when a row address strobe signal occurs, and said column addressing means is responsive to said column address when a column address strobe signal occurs.
Claim 4
Dependent Claim
48 words
A device according to claim 2 wherein said row address strobe signal has an activated condition and an inactivated condition, and wherein said address control input is a change of state of said column address strobe signal occurring when said row address storbe signal is said activated condition.
Claim 5
Dependent Claim
71 words
A device according to claim 1 wherein said column addressing means includes: a plurality of column address input buffer stages, one buffer stage for each bit of said column address, a plurality of column address latches, one for each stage of the buffer stages, each address latch having an input receiving an output of the buffer stage, the outputs of all of the address latch being coupled to column decoder means.
Claim 6
Dependent Claim
47 words
A device according to claim 4 wherein said address counter includes a plurality of counter stages, each counter stage having an input coupled to the output of one of said address latches and having an output coupled to the input of the one of said address latches.
Claim 7
Dependent Claim
18 words
A device according to claim 5 wherein each counter stage includes a counter latch and a carry circuit.
Claim 8
Dependent Claim
25 words
A device according to claim 6 wherein address bits propagate through said counter latch and carry circuit prior to occurrence of said address control input.
Claim 9
Dependent Claim
42 words
A device according to claim 5 wherein said row addressing means is responsive to said row address when a row address strobe signal occurs, and said column addressing means is responsive to said column address when a column address strobe signal occurs.
Claim 10
Dependent Claim
47 words
A device according to claim 8 wherein said row address strobe signal has an activated condition and an inactivated condition, and wherein said control input is a change of state of said column address strobe signals occurring when said row address strobe signal is said activated condition.
Claim 11
Dependent Claim
26 words
A device according to claim 1 wherein said memory device is a dynamic read/write memory, and said column addressing means produces column input and output data.
Claim 12
Independent Claim
180 words
A method of addressing a semiconductor memory device containing an array of rows and columns of memory cells, comprising the steps of: applying a row address to addressing means for the array at the time as a row address strobe is applied to said device, to select a row of the array for data input/output, applying a column address having a plurality of bits to column selector means for the array at the same time as a column address strobe is applied to said device, to select a plurality of columns from said selected row, while at the same time loading part of said bits of said column address into a counter register, said selected plurality of columns being available for data input/output, cycling said column address strobe between active and non-active conditions, and incrementing said counter register when said column address strobe is cycled between said conditions, coupling a selected one of said plurality of columns to an input/output terminal of the device in response to the contents of the counter register, during each cycle of the column address.
Claim 13
Independent Claim
180 words
A method of addressing a semiconductor memory device containing an array of rows and columns of memory cells, comprising the steps of: applying a row address to addressing means for the array at the time as a row address strobe is applied to said device, to select a row of the array for data input/output, applying a column address having a plurality of bits to column selector means for the array at the same time as a column address strobe is applied to said device, to select a plurality of columns from said selected row, while at the same time loading part of said bits of said column address into a counter register, said selected plurality of columns being available for data input/output, cycling said column address strobe between active and non-active conditions, and incrementing said counter register when said column address strobe is cycled between said conditions, coupling a selected one of said plurality of columns to an input/output terminal of the device in response to the contents of the counter register, during each cycle of the column address.
Claim 14
Dependent Claim
24 words
A method according to claim 11 wherein the step of cycling said column address strobe occurs when said row address strobe is continuously activated.
Claim 15
Dependent Claim
27 words
A method according to claim 11 wherein said memory cells are read/write memory cells, and said data output includes paths for both data input and data output.
Claim 16
Dependent Claim
13 words
A method according to claim 13 wherein said memory cells are dynamic cells.
Claim 17
Dependent Claim
120 words
A semiconductor dynamic read/write memory device comprising: an array of rows and columns of one-transistor dynamic storage cells, a differential sense amplifier for each column, row addressing means for activating one of said rows of storage cells at a first time in an operating cycle, means for activating said sense amplifiers for a sense period beginning at said first time in an operating cycle, column addressing means for selecting a plurality of said columns for data input or output in response to part of a multi-bit column address, a counter register loaded with a different part of said column address for selecting one of said plurality of columns for data input or output, and means for incrementing said counter register.
Claim 18
Dependent Claim
120 words
A semiconductor dynamic read/write memory device comprising: an array of rows and columns of one-transistor dynamic storage cells, a differential sense amplifier for each column, row addressing means for activating one of said rows of storage cells at a first time in an operating cycle, means for activating said sense amplifiers for a sense period beginning at said first time in an operating cycle, column addressing means for selecting a plurality of said columns for data input or output in response to part of a multi-bit column address, a counter register loaded with a different part of said column address for selecting one of said plurality of columns for data input or output, and means for incrementing said counter register.
Claim 19
Dependent Claim
29 words
A device according to claim 15 wherein said row addressing means includes a row address decoder producing a row address voltage only if a row address strobe is applied.
Claim 20
Dependent Claim
30 words
A device according to claim 16 wherein said column addressing means includes a plurality of column address buffers activated only if a column address strobe is applied to the device.
Claim 21
Dependent Claim
28 words
A device according to claim 17 wherein said means for incrementing is operated in response to toggling said column address strobe while said row address strobe is active.
References Cited (Backward Citations)
US4072932A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |