Integratable, bus-oriented transmission system

Claim 2

A monolithically integrated transmission system for binary information, comprising: at least one address source means connected via an address bus to at least one address sink means for creating selection signals; at least one register means connected to the address sink means for write-in and read-out of binary coded data and for activation by the selection signals via a control line, said register means being connected to a data bus; clock generator means for generating first and second phase shifted clock signals having non-overlapping activation levels; a first precharging means for precharging the address bus in accordance with the activation level of the first clock signal; a second precharging means for precharging the data bus in accordance with the activation level of said first clock signal; means for addressing said register means in accordance with the activation level of said second clock signal; and said one address source means charging the address bus with an address signal in a time between the activation levels of said first and second clock signals.

Claim 3

A transmission system according to claim 1 wherein an inhibit means is provided at each output of the address source means for inhibiting an address signal during the activation level of the first clock signal.

Claim 4

A transmission system according to claim 1 wherein an inhibit circuit means is provided at an output of the address sink for inhibiting selection signals during the activation level of the first clock signal.

Claim 5

A transmission system according to claim 2 wherein the inhibit circuit means comprises a NOR gate which is connected at an input side to the address source means and to the first clock line.

Claim 6

A transmission system according to claim 1 wherein said clock generator means connects to an output of a control loop circuit means for emitting a control signal to influence beginning of the second clock signal at the clock generator means; said control loop circuit means comprising a control line which is prechargeable by a third precharging means during the activation level of the first clock signal; said control loop circuit means having means for simulating a transit time behavior of the address bus, said means including at least one delay means; and said control loop circuit means having a discharge means for discharging the control line at an end of the activation level of the first clock signal.

Claim 7

A monolithically integrated transmission system for binary information, comprising: at least one address source means connected via an address bus to at least one address sink means for creating selection signals; at least one register means for write-in and read-out of binary coded data connected to the address sink means, said register means being activated by the selection signals via a respective control line, said register means being connected to a data bus; clock generator means for generating first and second phase shifted clock signals having respective activation levels which are non-overlapping; a first precharging means for precharging the control line in accordance with the activation level of the first clock signal; a second precharging means for precharging the data bus in accordance with the activation level of said first clock signal; means for addressing said register means in accordance with the activation level of said second clock signal; and said at least one address source means charging the address bus with the selection signals in a time between activation levels of said first and second clock signals.

Claim 8

A monolithically integrated transmission system for binary information, comprising: at least one address source means connected via an address bus to at least one address sink means for creating selection signals; at least one register means for write-in and read-out of binary coded data connected to the address sink means, said register means being activated by the selection signals via a respective control line, said register means being connected to a data bus; clock generator means for generating first and second phase shifted clock signals having respective activation levels which are non-overlapping; a first precharging means for precharging the control line in accordance with the activation level of the first clock signal; a second precharging means for precharging the data bus in accordance with the activation level of said first clock signal; means for addressing said register means in accordance with the activation level of said second clock signal; and said at least one address source means charging the address bus with the selection signals in a time between activation levels of said first and second clock signals.

Claim 9

A transmission system according to claim 6 wherein an inhibit circuit means is provided at an output of the address bus for inhibiting a selection signal during the activation level of the first clock signal.

Claim 10

A transmission system according to claim 7 wherein the inhibit circuit means comprises a NOR gate which is connected at an input side to the address bus and to the first clock line.

Claim 11

A transmission system according to claim 6 wherein said clock generator means connects to an output of a control loop circuit means for emitting a control signal to influence beginning of the second clock signal at the clock generator means; said control loop circuit means having means for simulating a transit time behavior of the control line said means including at least one delay means, and said control means having a discharge means for discharging a duplicate control line in dependence upon the first clock signal.