Bitline pull-up circuit for a BiCMOS read/write memory

Claim 2

A read/write memory device of the type having an array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and for selecting a row in said said array of memory cells responsive thereto, and a column decoder for receiving a column address signal and for selecting a column in said array of memory cells responsive thereto, said read/write memory device operable to present the data of a memory cell in the selected column which is in the selected row during a read operation, and to write input data to a memory cell in the selected column which is in the selected row during a write operation, wherein each column of memory cells in said array share true and complement bit lines, said memory device further comprising: a sense amplifier in communication with the bit lines of the column of said array selected by said column decoder for sensing the data stored in the memory cell in said selected column which is in said selected row; write circuitry for biasing the true bit line in the selected column to a predetermined voltage responsive to the input data at a first logic state in a write operation, and for biasing the complement bit line in the selected column to said predetermined voltage responsive to the input data at a second logic state in a write operation; a first pull-up transistor for each true bit line in each column, each said first pull-up transistor having its emitter connected to its associated true bit line and its collector connected to a power supply node, and having a base; a second pull-up transistor for each complement bit line in each column, each said second pull-up transistor having its emitter connected to its associated complement bit line and its collector connected to said power supply node, and having a base; pull-up control circuitry connected to the bases of said first and second pull-up transistors, so that both said first and second pull-up transistors are biased to an on-state in a read operation, and so that in a write operation one of said first or second pull-up transistors in the selected column is biased on to a lower voltage than the on-state in a read operation and the other is biased off, depending upon the logic state of said input data.

Claim 3

The read/write memory device of claim 1, wherein a sense amplifier is provided for each column in said array.

Claim 4

The read/write memory device of claim 1, wherein said write circuitry biases said true bit line in the selected column to a low voltage responsive to the input data at a first logic state in a write operation, and biases the complement bit line in the selected column to a low voltage responsive to the input data at a second logic state in a write operation.

Claim 5

The read/write memory device of claim 3, wherein said pull-up control circuitry biases said first pull-up transistor in said selected column off, and biases said second pull-up transistor in said selected column to a lower voltage than the on-state in a read operation responsive to the input data at said first logic state, and wherein said pull-up control circuitry biases said second pull-up transistor in said selected column off, and biases said first pull-up transistor in said selected column to a lower voltage than the on-state in a read operation responsive to the input data at said second logic state.

Claim 6

The read/write memory device of claim 1, wherein said pull-up control circuitry also, in a write operation, biases one of said first and second pull-up transistors in an unselected column on to a lower voltage than the on-state in a read operation and biases the other off, depending upon the logic state of said input data.

Claim 7

The read/write memory device of claim 1, wherein said pull-up control circuitry also filters noise on said power supply node from the bases of said first and second pull-up transistors in a read operation.

Claim 8

The read/write memory device of claim 1, wherein said pull-up control circuitry comprises: a first block for biasing the base of said first pull-up transistors, having a data input for receiving a data-in signal, a feedback input a feedback output, and a bias output connected to said base of said first pull-up transistors; and a second block for biasing the base of said second pull-up transistors, having a data input for receiving the complement of the data-in signal received by said first block, having a feedback input connected to the feedback output of said first block, having a feedback output connected to the feedback input of said second block , and having a bias output connected to the base o said second pull-up transistors.

Claim 9

The read/write memory device of claim 7, wherein said pull-up control circuitry further comprises a low-pass filter connected to said power supply node and to the bias outputs of said first and second blocks.

Claim 10

The read/write memory device of claim 7, wherein each of said first and second blocks comprise: a pull-down circuit, connected between a reference supply node and said bias output and controlled by said data input, for pulling down the bias output to said reference supply node responsive to said data input at a first logic state; a feedback circuit, connected to said data input, for presenting a signal at said feedback output corresponding to the data state of said data input; a first pull-up circuit, connected between said power supply node and said bias node, for pulling up the bias output to said power supply node responsive to said data input at a second logic state, and responsive to said feedback input indicating that said data input of the other block is at said second logic state; a second pull-up circuit, connected between said power supply node and said bias node, for biasing the bias output to a lower level than said first pull-up circuit responsive to said data input at said second logic state and said feedback input indicating that said data input of the other block is at said first logic state.

Claim 11

The read/write memory device of claim 9, wherein said second pull-up circuit comprises: a bipolar drive transistor having its collector connected to said power supply node, its emitter connected to said bias node, and its base responsively coupled to said data input to turn said bipolar drive transistor on responsive to said data input at said second logic state; a field effect load transistor having its source-to-drain path connected between said bias node and said reference supply node, and having a gate; logic having a first input connected to said feedback input and a second input responsively coupled to said data input, and having an output connected to the gate of said field effect load transistor so that said field effect load transistor is turned on responsive to said data input at said second logic state and said feedback input indicating that the data input of the other block is at said first logic state.

Claim 12

The read/write memory of claim 10, wherein said logic turns off said field effect transistor responsive to said data input at said second logic state and said feedback input indicating that the data input of the other block is at said second logic state.

Claim 13

In a read/write memory of the type having an array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and for selecting a row in said said array of memory cells responsive thereto, a column decoder for receiving a column address signal and for selecting a column in said array of memory cells responsive thereto, sense and output circuitry for presenting the data of a memory cell in the selected column which is in the selected row during a read operation, and write circuitry for writing input data to a memory cell in the selected column which is in the selected row during a write operation, wherein each column of memory cells in said array share true and complement bit lines, the improvement comprising: a first pull-up transistor for each true bit line in each column, each said first pull-up transistor having its emitter connected to its associated true bit line and its collector connected to a power supply node, and having a base; a second pull-up transistor for each complement bit line in each column, each said second pull-up transistor having its emitter connected to its associated complement bit line and its collector connected to said power supply node, and having a base; and pull-up control circuitry connected to the bases of said first and second pull-up transistors, comprising: bias circuitry connected to said bases of said first and second pull-up transistors so that both said first and second pull-up transistors are biased to an on-state in a read operation; and a low-pass filter connected between said power supply node and said bases of said first and second pull-up transistors.

Claim 14

In a read/write memory of the type having an array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and for selecting a row in said said array of memory cells responsive thereto, a column decoder for receiving a column address signal and for selecting a column in said array of memory cells responsive thereto, sense and output circuitry for presenting the data of a memory cell in the selected column which is in the selected row during a read operation, and write circuitry for writing input data to a memory cell in the selected column which is in the selected row during a write operation, wherein each column of memory cells in said array share true and complement bit lines, the improvement comprising: a first pull-up transistor for each true bit line in each column, each said first pull-up transistor having its emitter connected to its associated true bit line and its collector connected to a power supply node, and having a base; a second pull-up transistor for each complement bit line in each column, each said second pull-up transistor having its emitter connected to its associated complement bit line and its collector connected to said power supply node, and having a base; and pull-up control circuitry connected to the bases of said first and second pull-up transistors, comprising: bias circuitry connected to said bases of said first and second pull-up transistors so that both said first and second pull-up transistors are biased to an on-state in a read operation; and a low-pass filter connected between said power supply node and said bases of said first and second pull-up transistors.

Claim 15

The improved read/write memory device of claim 12, wherein said bias circuitry also is responsive to input data to the memory device, so that in a write operation one of said first or second pull-up transistors in the selected column is biased on to a lower voltage than the on-state in a read operation and the other is biased off, depending upon the logic state of said input data.

Claim 16

The improved read/write memory device of claim 13, wherein said bias circuitry comprises: a first block for biasing the base of said first pull-up transistors, having a data input for receiving a data-in signal, a feedback input a feedback output, and a bias output connected to said base of said first pull-up transistors; and a second block for biasing the base of said second pull-up transistors, having a data input for receiving the complement of the data-in signal received by said first block, having a feedback input connected to the feedback output of said first block, having a feedback output connected to the feedback input of said second block , and having a bias output connected to the base of said second pull-up transistors.

Claim 17

The improved read/write memory device of claim 14, wherein each of said first and second blocks comprise: a pull-down circuit, connected between a reference supply node and said bias output and controlled by said data input, for pulling down the bias output to said reference supply node responsive to said data input at a first logic state; a feedback circuit, connected to said data input, for presenting a signal at said feedback output corresponding to the data state of said data input; a first pull-up circuit, connected between said power supply node and said bias node, for pulling up the bias output to said power supply node responsive to said data input at a second logic state, and responsive to said feedback input indicating that said data input of the other block is at said second logic state; a second pull-up circuit, connected between said power supply node and said bias node, for biasing the bias output to a lower level than said first pull-up circuit responsive to said data input at said second logic state and said feedback input indicating that said data input of the other block is at said first logic state.

Claim 18

The improved read/write memory device of claim 15, wherein said low-pass filter is contained within said first pull-up circuit of one of said blocks.

Claim 19

The improved read/write memory device of claim 15, wherein said second pull-up circuit comprises: a bipolar drive transistor having its collector connected to said power supply node, its emitter connected to said bias node, and its base responsively coupled to said data input to turn said bipolar drive transistor on responsive to said data input at said second logic state; a field effect load transistor having its source-to-drain path connected between said bias node and said reference supply node, and having a gate; logic having a first input connected to said feedback input and a second input responsively coupled to said data input, and having an output connected to the gate of said field effect load transistor so that said field effect load transistor is turned on responsive to said data input at said second logic state and said feedback input indicating that the data input of the other block is at said first logic state.

Claim 20

The improved read/write memory of claim 17, wherein said logic turns off said field effect transistor responsive to said data input at said second logic state and said feedback input indicating that the data input of the other block is at said second logic state.

Claim 21

The improved read/write memory of claim 20, wherein said first and second blocks each further comprise: a filter connect transistor having a source-to-drain path connected between a filter node and said bias output, and having a gate connected to the output of said logic so that said filter connect transistor disconnects said filter node to said bias output responsive to either said data input at said first logic state or said feedback input indicating that the data input of the other block is at said first logic state; wherein said first block further comprises said low-pass filter, comprising: a resistor connected between a filter node and said power supply node; and a capacitor connected between said filter node and said reference supply node; and wherein said filter node of said first block is connected to the filter node of said second block.

Claim 22

A read/write memory device of the type having an array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and for selecting a row in said said array of memory cells responsive thereto, and a column decoder for receiving a column address signal and for selecting a column in said array of memory cells responsive thereto, said read/write memory device operable to present the data of a memory cell in the selected column which is in the selected row during a read operation, and to write input data to a memory cell in the selected column which is in the selected row during a write operation, wherein each column of memory cells in said array share true and complement bit lines, said memory device further comprising: a sense amplifier in communication with the bit lines of the column of said array selected by said column decoder for sensing the data stored in the memory cell in said selected column which is in said selected row; write circuitry for biasing the true bit line in the selected column to a predetermined voltage responsive to the input data at a first logic state in a write operation, and for biasing the complement bit line in the selected column to said predetermined voltage responsive to the input data at a second logic state in a write operation; a first pull-up transistor for each true bit line in each column, each said first pull-up transistor having its emitter connected to its associated true bit line and its collector connected to a power supply node, and having a base; a second pull-up transistor for each complement bit line in each column, each said second pull-up transistor having its emitter connected to its associated complement bit line and its collector connected to said power supply node, and having a base; pull-up control circuitry connected to the bases of said first and second pull-up transistors, so that both said first and second pull-up transistors are biased to an on-state in a read operation, and so that in a write operation one of said first or second pull-up transistors in the selected column is biased on to a lower voltage than the on-state in a read operation and the other is biased off, depending upon the logic state of said input data, said pull-up control circuitry comprising: a first block for biasing the base of said first pull-up transistors, having a data input for receiving a first data-in signal, a feedback input, a delayed feedback output for presenting a delayed signal corresponding to the logic state of said data-in signal, and a bias output connected to said base of said first pull-up transistors; and a second block for biasing the base of said second pull-up transistors, having a data input for receiving a second data-in signal, having a feedback input connected to the feedback output of said first block, having a feedback output connected to the feedback input of said first block, for presenting a delayed signal corresponding to the logic state of said second data-in signal, and having a bias output connected to the base of said second pull-up transistors.

Claim 23

A read/write memory device of the type having an array of memory cells arranged in rows and columns, a row decoder for receiving a row address signal and for selecting a row in said said array of memory cells responsive thereto, and a column decoder for receiving a column address signal and for selecting a column in said array of memory cells responsive thereto, said read/write memory device operable to present the data of a memory cell in the selected column which is in the selected row during a read operation, and to write input data to a memory cell in the selected column which is in the selected row during a write operation, wherein each column of memory cells in said array share true and complement bit lines, said memory device further comprising: a sense amplifier in communication with the bit lines of the column of said array selected by said column decoder for sensing the data stored in the memory cell in said selected column which is in said selected row; write circuitry for biasing the true bit line in the selected column to a predetermined voltage responsive to the input data at a first logic state in a write operation, and for biasing the complement bit line in the selected column to said predetermined voltage responsive to the input data at a second logic state in a write operation; a first pull-up transistor for each true bit line in each column, each said first pull-up transistor having its emitter connected to its associated true bit line and its collector connected to a power supply node, and having a base; a second pull-up transistor for each complement bit line in each column, each said second pull-up transistor having its emitter connected to its associated complement bit line and its collector connected to said power supply node, and having a base; pull-up control circuitry connected to the bases of said first and second pull-up transistors, so that both said first and second pull-up transistors are biased to an on-state in a read operation, and so that in a write operation one of said first or second pull-up transistors in the selected column is biased on to a lower voltage than the on-state in a read operation and the other is biased off, depending upon the logic state of said input data, said pull-up control circuitry comprising: a first block for biasing the base of said first pull-up transistors, having a data input for receiving a first data-in signal, a feedback input, a delayed feedback output for presenting a delayed signal corresponding to the logic state of said data-in signal, and a bias output connected to said base of said first pull-up transistors; and a second block for biasing the base of said second pull-up transistors, having a data input for receiving a second data-in signal, having a feedback input connected to the feedback output of said first block, having a feedback output connected to the feedback input of said first block, for presenting a delayed signal corresponding to the logic state of said second data-in signal, and having a bias output connected to the base of said second pull-up transistors.

Claim 24

The memory of claim 20, wherein, for a write operation, the first and second data-in signals presented to said first and second blocks are the logical complement of one another.

Claim 25

The memory of claim 21, wherein, for a read operation, the first and second data-in signals presented to said first and second blocks are at the same data state.

Claim 26

The memory of claim 20, wherein each of said first and second blocks comprise: a pull-down circuit, connected between a reference supply node and said bias output and controlled by said data input, for pulling down the bias output to said reference supply node responsive to said data input at a first logic state; a feedback circuit, connected to said data input, for presenting a signal at said feedback output corresponding to the data state of said data input, delayed by a predetermined time; a first pull-up circuit, connected between said power supply node and said bias node, for pulling up the bias output to said power supply node responsive to said data input at a second logic state, and responsive to said feedback input indicating that said data input of the other block is at said second logic state; a second pull-up circuit, connected between said power supply node and said bias node, for biasing the bias output to a lower level than said first pull-up circuit responsive to said data input at said second logic state and said feedback input indicating that said data input of the other block is at said first logic state.

Claim 27

The memory of claim 23, wherein the predetermined delay time of said feedback output in each block is such that the first pull-up circuit is not turned on responsive to its feedback input indicating that said data input of the other block is at said second logic state until after such time as the bias output of the other block has been pulled up by its second pull-up circuit most of the way to said lower level.