Sense amplifier for a semiconductor memory device

Claim 2

A sense amplifier circuit comprising (a) first and second input lines to which voltages with a difference therebetween are to be applied respectively, (b) a differential amplifier provided between sources of voltages of high and low levels and having a pair of input terminals respectively connected to said first and second input lines, (c) first and second inverter means each having an input terminal and an output terminal, the input terminal of the first inverter means being connected to said first input line and the input terminal of the second inverter means being connected to said second input line, (d) a first transistor having a current path provided between said first input line and the source of said voltage of low level and a control terminal connected to the output terminal of said first inverter means, and (e) a second transistor having a current path provided between said second input line and the source of said voltage of low level and a control terminal connected to the output terminal of said second inverter means.

Claim 3

A differential amplifier circuit comprising (a) first and second input lines to which potentials with a difference therebetween are to be applied respectively, (b) a series combination of a first load transistor and a first amplifier transistor having respective current paths connected in series between a source of a voltage of high level and said common node, (c) a series combination of a second load transistor and a second amplifier transistor having respective current paths connected in series between a source of a voltage of low level and said common node, and (d) activating means having a current path connected between said common node and said source of the voltage of low level for activating each of the first and second amplifier transistors when said current path of said activating means is conductive, (e) each of said first and second load transistors and said first and second amplifier transistors having input and output terminals and a control terminal, the control terminals of the first and second amplifier transistors being biased to render said first and second load transistors conductive, the control terminal of said first amplifier transistor being connected to said first input line and the control terminal of said second amplifier transistor being connected to said second input line, (f) first and second inverter means each having an input terminal and an output terminal, the input terminal of the first inverter means being connected to said first input line and the input terminal of the second inverter means being connected to said second input line, (g) a first transistor having a current path provided between said first input line and the source of said voltage of low level and a control terminal connected to the output terminal of said first inverter means, and (h) a second transistor having a current path provided between said second input line and the source of said voltage of low level and a control terminal connected to the output terminal of said second inverter means, and (i) means for controlling said activating means.

Claim 4

A differential amplifier circuit comprising (a) first and second input lines to which potentials with a difference therebetween are to be applied respectively, (b) a series combination of a first load transistor and a first amplifier transistor having respective current paths connected in series between a source of a voltage of high level and said common node, (c) a series combination of a second load transistor and a second amplifier transistor having respective current paths connected in series between a source of a voltage of low level and said common node, and (d) activating means having a current path connected between said common node and said source of the voltage of low level for activating each of the first and second amplifier transistors when said current path of said activating means is conductive, (e) each of said first and second load transistors and said first and second amplifier transistors having input and output terminals and a control terminal, the control terminals of the first and second amplifier transistors being biased to render said first and second load transistors conductive, the control terminal of said first amplifier transistor being connected to said first input line and the control terminal of said second amplifier transistor being connected to said second input line, (f) first and second inverter means each having an input terminal and an output terminal, the input terminal of the first inverter means being connected to said first input line and the input terminal of the second inverter means being connected to said second input line, (g) a first transistor having a current path provided between said first input line and the source of said voltage of low level and a control terminal connected to the output terminal of said first inverter means, and (h) a second transistor having a current path provided between said second input line and the source of said voltage of low level and a control terminal connected to the output terminal of said second inverter means, and (i) means for controlling said activating means.

Claim 5

A differential amplifier circuit as set forth in claim 1 or 2, wherein each of said first and second inverter means comprises a CMOS (complementary metal-oxide-semiconductor) inverter circuit.

Claim 6

A differential amplifier circuit comprising (a) first and second input lines to which potentials with a difference therebetween are to be applied respectively, (b) a first series combination of load and amplifier transistors each having a current path and a control terminal, (c) a second series combination of load and amplifier transistors each having a current path and a control terminal, (d) an activating transistor having a current path and a control terminal, (e) the load and amplifier transistors of each of said first and second series combinations having their respective current paths connected between sources of voltages of high and low levels through the current path of said activating transistor, the respective load transistors of said first and second series combinations having their control terminals coupled together to a predetermined potential, the amplifier transistor of said first series combination having its control terminal connected to said first input line and the amplifier transistor of said second series combination having its control terminal connected to said second input line, (f) first and second inverter means each having an input terminal and an output terminal, the input terminal of the first inverter means being connected to said first input line and the input terminal of the second inverter means connected to said second input line, (g) a first transistor having a current path connected between said first input line and the source of said voltage of low level and a control terminal connected to the output terminal of said first inverter means, (h) a second transistor having a current path connected between said second input line and the source of said voltage of low level and a control terminal connected to the output terminal of said second inverter means, and (i) means for controlling said activating transistor.

Claim 7

A differential amplifier circuit comprising (a) first and second input lines to which potentials with a difference therebetween are to be applied respectively, (b) a first series combination of load and amplifier transistors each having a current path and a control terminal, (c) a second series combination of load and amplifier transistors each having a current path and a control terminal, (d) an activating transistor having a current path and a control terminal, (e) the load and amplifier transistors of each of said first and second series combinations having their respective current paths connected between sources of voltages of high and low levels through the current path of said activating transistor, the respective load transistors of said first and second series combinations having their control terminals coupled together to a predetermined potential, the amplifier transistor of said first series combination having its control terminal connected to said first input line and the amplifier transistor of said second series combination having its control terminal connected to said second input line, (f) first and second inverter means each having an input terminal and an output terminal, the input terminal of the first inverter means being connected to said first input line and the input terminal of the second inverter means connected to said second input line, (g) a first transistor having a current path connected between said first input line and the source of said voltage of low level and a control terminal connected to the output terminal of said first inverter means, (h) a second transistor having a current path connected between said second input line and the source of said voltage of low level and a control terminal connected to the output terminal of said second inverter means, and (i) means for controlling said activating transistor.

Claim 8

A differential amplifier circuit comprising (a) first and second signal lines to which potential with a difference therebetween are to be applied respectively, (b) a differential amplifier having first and second input terminals, (c) means for connecting said first input terminal to said first signal line, (d) means for connecting said second input terminal to said second signal line, (e) a first discharge circuit connected between said first signal line and a reference voltage source for releasing charges through said first signal line toward said reference voltage source, (f) a second discharge circuit connected between said second signal line and said reference voltage source for releasing charges through said second signal line toward said reference voltage source, (g) a first control circuit connected to said first signal line and to said first discharge circuit for selectively enabling said first discharge circuit when a potential on said first signal line is lower than a predetermined level, (h) a second control circuit connected to said second signal line and to said second discharge circuit for selectively enabling said second discharge circuit when a potential on said second signal line is lower than said predetermined level, and (i) means for enabling said differential amplifier when one of said first and second discharge circuits is enabled.

Claim 9

A differential amplifier circuit comprising (a) first and second signal lines to which potential with a difference therebetween are to be applied respectively, (b) a differential amplifier having first and second input terminals, (c) means for connecting said first input terminal to said first signal line, (d) means for connecting said second input terminal to said second signal line, (e) a first discharge circuit connected between said first signal line and a reference voltage source for releasing charges through said first signal line toward said reference voltage source, (f) a second discharge circuit connected between said second signal line and said reference voltage source for releasing charges through said second signal line toward said reference voltage source, (g) a first control circuit connected to said first signal line and to said first discharge circuit for selectively enabling said first discharge circuit when a potential on said first signal line is lower than a predetermined level, (h) a second control circuit connected to said second signal line and to said second discharge circuit for selectively enabling said second discharge circuit when a potential on said second signal line is lower than said predetermined level, and (i) means for enabling said differential amplifier when one of said first and second discharge circuits is enabled.

Claim 10

A differential amplifier circuit as set forth in claim 5, in which each of said first and second discharge circuits has a control terminal and in which each of said first and second control circuits comprises an inverter having an input terminal connected to one of said first and second signal lines and an output terminal connected to the control terminal of one of said first and second discharge circuits.

Claim 11

A differential amplifier circuit as set forth in claim 6, in which said differential amplifier comprises: a first series circuit of a load element and a transistor having respective current paths connected in series between a power supply terminal and a common node, a second series circuit of a load element and a transistor having respective current paths connected in series between said power supply terminal and said common node, and a transistor having a current path connected in series between said common node and said reference voltage source.

Claim 12

A differential amplifier circuit as set forth in claim 5, in which each of said first and second discharge circuit comprises a discharge transistor having a current path and a control terminal and means for having the current path of the discharge transistor of each discharge circuit connected between one of said first and second signal lines and said reference voltage source.