Reduced power sense amplifier

Claim 2

An amplifier, comprising: a first differential amplifier for providing first and second control signals in response to a pair of input signals; a second differential amplifier for receiving the pair of input signals and for providing output signals in response thereto; first variable load means, coupled to a first power supply terminal and the second differential amplifier, for providing a load capable of carrying a current proportional to and in response to the first control signal; and second variable load means, coupled to the first power supply terminal and the second differential amplifier, for providing a load capable of carrying a current proportional to and in response to the second control signal.

Claim 3

The amplifier of claim 1, wherein the second differential amplifier comprises: a first transistor having a control electrode for receiving a first of the pair of input signals, a first current electrode for providing the first output signal, and a second current electrode; a second transistor having a control electrode for receiving a second of the pair of input signals, a first current electrode for providing the second output signal, and a second current electrode coupled to the second current electrode of the first transistor; and a first current source coupled between the second current electrode of the first transistor and a second power supply terminal.

Claim 4

The amplifier of claim 2, wherein the first and second transistors have gains which are matched.

Claim 5

The amplifier of claim 3, wherein the first variable load means comprises a third transistor having a control electrode for receiving the first control signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the first current electrode of the first transistor.

Claim 6

The amplifier of claim 4, wherein the second variable load means comprises a fourth transistor having a control electrode for receiving the second control signal, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the first current electrode of the second transistor.

Claim 7

The amplifier of claim 5, wherein the third and fourth transistors have gains which are matched.

Claim 8

The amplifier of claim 6, wherein the first and second transistors are of a first conductivity type, and the third and fourth transistors are of a second conductivity type.

Claim 9

The amplifier of 7, wherein the first differential amplifier comprises: a fifth transistor having a control electrode for receiving the first of the pair of input signals, a first current electrode for providing the second control signal, and a second current electrode: a sixth transistor having a control electrode for receiving the second of the pair of input signals, a first current electrode for providing the first control signal, and a second current electrode coupled to the second current electrode of the fifth transistor; and a second current source coupled between the second current electrode of the fifth transistor and the second power supply terminal.

Claim 10

The amplifier of 7, wherein the first differential amplifier comprises: a fifth transistor having a control electrode for receiving the first of the pair of input signals, a first current electrode for providing the second control signal, and a second current electrode: a sixth transistor having a control electrode for receiving the second of the pair of input signals, a first current electrode for providing the first control signal, and a second current electrode coupled to the second current electrode of the fifth transistor; and a second current source coupled between the second current electrode of the fifth transistor and the second power supply terminal.

Claim 11

The amplifier of claim 8, wherein the fifth and sixth transistors have gains which are matched.

Claim 12

The amplifier of claim 9 further comprising: a seventh transistor having a control electrode and a first current electrode coupled to the first current electrode of the fifth transistor, and a second current electrode coupled to the first power supply terminal; and an eighth transistor having a control electrode and a first current electrode coupled to the first current electrode of the sixth transistor, and a second current electrode coupled to the first power supply terminal.

Claim 13

The amplifier of claim 10, wherein the seventh and eighth transistors have gains which are matched.

Claim 14

The amplifier of claim 11, wherein the fifth and sixth transistors are of the first conductivity type, and the seventh and eighth transistors are of the second conductivity type.

Claim 15

The amplifier of claim 2, wherein the first differential amplifier comprises: a third transistor having a control electrode for receiving the first of the pair of input signals, a first current electrode for providing the second control signal, and a second current electrode; a fourth transistor having a control electrode for receiving the second of the pair of input signals, a first current electrode for providing the first control signal, and a second current electrode coupled to the second current electrode of the third transistor; and a second current source coupled between the second current electrode of the third transistor and the second power supply terminal.

Claim 16

The amplifier of claim 13, further comprising: a first load coupled between the first power supply terminal and the first current electrode of the third transistor; and a second load coupled between the first power supply terminal and the first current electrode of the fourth transistor.

Claim 17

In an amplifier having first and second differential amplifiers and first and second current mirrors for loads for the differential amplifiers, the improvement characterized by: the first differential amplifier receiving complementary input signals; the second differential amplifier receiving the complementary input signals; the first current mirror having a master section and a slave section, the master section providing a first load for the first differential amplifier and the slave section, in response to said master section load current, providing a second load for the second differential amplifier; and the second current mirror having a master section and a slave section, the master section providing a second load for the first differential amplifier and the slave section, in response to its respective master section load current, providing a first load for the second differential amplifier.

Claim 18

In an amplifier having first and second differential amplifiers and first and second current mirrors for loads for the differential amplifiers, the improvement characterized by: the first differential amplifier receiving complementary input signals; the second differential amplifier receiving the complementary input signals; the first current mirror having a master section and a slave section, the master section providing a first load for the first differential amplifier and the slave section, in response to said master section load current, providing a second load for the second differential amplifier; and the second current mirror having a master section and a slave section, the master section providing a second load for the first differential amplifier and the slave section, in response to its respective master section load current, providing a first load for the second differential amplifier.

Claim 19

In an amplifier, comprising: a first differential amplifier for providing first and second control signals in response to input signals having a voltage differential; a second differential amplifier for receiving the input signals and for providing complementary output signals in response thereto; a first load of variable conductivity coupled between the first power supply terminal and the second differential amplifier; and a second load of variable conductivity coupled between the first power supply terminal and the second differential amplifier; a method comprising the steps of: varying the conductivity of the first load in response to the first control signal; and varying the conductivity of the second load in response to the second control signal.

Claim 20

In an amplifier, comprising: a first differential amplifier for providing first and second control signals in response to input signals having a voltage differential; a second differential amplifier for receiving the input signals and for providing complementary output signals in response thereto; a first load of variable conductivity coupled between the first power supply terminal and the second differential amplifier; and a second load of variable conductivity coupled between the first power supply terminal and the second differential amplifier; a method comprising the steps of: varying the conductivity of the first load in response to the first control signal; and varying the conductivity of the second load in response to the second control signal.

Claim 21

An amplifier, comprising: a sense amplifier, for providing a pair of complementary intermediate output signals in response to a pair of complementary input signals, the sense amplifier having a pair of differential amplifiers comprised of transistors of a first conductivity type and a pair of transistor loads of a second conductivity type; and a secondary amplifier, for providing complementary output signals in response to receiving the complementary intermediate output signals, the secondary amplifier having a pair of differential amplifiers comprised of transistors of the second conductivity type and a pair of transistor loads of the first conductivity type.

Claim 22

An amplifier, comprising: a sense amplifier, for providing a pair of complementary intermediate output signals in response to a pair of complementary input signals, the sense amplifier having a pair of differential amplifiers comprised of transistors of a first conductivity type and a pair of transistor loads of a second conductivity type; and a secondary amplifier, for providing complementary output signals in response to receiving the complementary intermediate output signals, the secondary amplifier having a pair of differential amplifiers comprised of transistors of the second conductivity type and a pair of transistor loads of the first conductivity type.