Memory device with variable load

Claim 2

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells operably connected to said word lines and said digit lines, a plurality of load means arranged between said digit lines and a predetermined potential, said load means having controllable value of conductance, means for supplying a control signal having a first level designating a write operation for writing a first logical data in selected one of said memory cells and a second level for designating a read operation for reading out a logical data opposite to said first logical data from another selected one of said memory cells, detection means for detecting a transition in said control signal from said first level to said second level, said detection means generating an output signal of a third level over a predetermined period when said transition is detected, and means responsive to said output signal of said third level from said detection means for enhancing the conductance of said load means.

Claim 3

The memory device of claim 1, wherein said first logical data is a logical "0".

Claim 4

A memory device comprising a plurality of word lines; a plurality of digit line pairs; a plurality of memory cells, each of said memory cells comprising two pairs of field effect transistors, each pair serially connected between a first and a second potential source, each pair of said field effect transistors having their drains commonly connected, the gates of the first and second pair respectively connected to the drains of the second and the first pair of said field effect transistors, a pair of transfer gate field effect transistors, each respectively connected between the connecting point of the drains of each of said pairs of field effect transistors and a respective digit line, the gates of said pair of transfer gate field effect transistor connected to a respective word line; a plurality of first load field effect transistors arranged between a voltage supply means and the respective digit lines, a plurality of second load field effect transistors arranged between the voltage supply means and the respective digit lines; means for supplying a control signal having first and second levels to a control terminal; a write circuit for performing a write operation in response to said first level signal for a selected memory cell; a read circuit for performing a read operation for another selected memory cell in response to said second level signal; a change detection circuit for detecting a transition from said first level signal to said second level signal, said change detection circuit generating a detection signal over a predetermined period, said change detection circuit including a series circuit of a plurality of inverter circuits for transmitting said control signal from its input terminal to its output terminal and gate means for detecting a transit period when said control signal is transmitted from said input terminal of said series circuit to said output terminal of said series circuit, said detection signal being generated when said transit period is detected; means for rendering conductive said plurality of second load field effect transistors while said detection signal is present, and means for rendering conductive said plurality of first load field effect transistors irrespective of said detection signal.

Claim 5

A memory device comprising a plurality of word lines; a plurality of digit line pairs; a plurality of memory cells, each of said memory cells comprising two pairs of field effect transistors, each pair serially connected between a first and a second potential source, each pair of said field effect transistors having their drains commonly connected, the gates of the first and second pair respectively connected to the drains of the second and the first pair of said field effect transistors, a pair of transfer gate field effect transistors, each respectively connected between the connecting point of the drains of each of said pairs of field effect transistors and a respective digit line, the gates of said pair of transfer gate field effect transistor connected to a respective word line; a plurality of first load field effect transistors arranged between a voltage supply means and the respective digit lines, a plurality of second load field effect transistors arranged between the voltage supply means and the respective digit lines; means for supplying a control signal having first and second levels to a control terminal; a write circuit for performing a write operation in response to said first level signal for a selected memory cell; a read circuit for performing a read operation for another selected memory cell in response to said second level signal; a change detection circuit for detecting a transition from said first level signal to said second level signal, said change detection circuit generating a detection signal over a predetermined period, said change detection circuit including a series circuit of a plurality of inverter circuits for transmitting said control signal from its input terminal to its output terminal and gate means for detecting a transit period when said control signal is transmitted from said input terminal of said series circuit to said output terminal of said series circuit, said detection signal being generated when said transit period is detected; means for rendering conductive said plurality of second load field effect transistors while said detection signal is present, and means for rendering conductive said plurality of first load field effect transistors irrespective of said detection signal.

Claim 6

The memory device according to claim 3, wherein the number of said inverter circuits is an odd number and said gate means includes a NOR circuit having a first input terminal connected to said input terminal of said series circuit and a second input terminal connected to said output terminal of said series circuit.

Claim 7

A memory device comprising a plurality of address lines, a plurality of digit lines, a plurality of static memory cells operably connected to said address lines and said digit lines, a plurality of address terminals for receiving a plurality of address signals, means for providing said address signals, a control terminal for receiving a control signal having a first level and a second level, means for providing said control signal, a mode select circuit producing a write enable signal in response to said first level signal and a read enable signal in response to said second level signal, a write circuit for providing selected digit line with a logic information to be written in response to said write enable signal, a control circuit for producing a write end signal when said control signal changes from said first level to said second level, a plurality of resistive elements arranged between said digit lines and a predetermined potential, and a plurality of field effect transistors arranged between said digit lines and said predetermined potential and in parallel with said resistive elements, the gates of said field effect transistors being supplied with said write end signal, in which effective resistance between said digit line and said predetermined potential is lowered in a transition period that the operation is shifted from a write operation to a read operation.

Claim 8

A memory device comprising a plurality of address lines, a plurality of digit lines, a plurality of static memory cells operably connected to said address lines and said digit lines, a plurality of address terminals for receiving a plurality of address signals, means for providing said address signals, a control terminal for receiving a control signal having a first level and a second level, means for providing said control signal, a mode select circuit producing a write enable signal in response to said first level signal and a read enable signal in response to said second level signal, a write circuit for providing selected digit line with a logic information to be written in response to said write enable signal, a control circuit for producing a write end signal when said control signal changes from said first level to said second level, a plurality of resistive elements arranged between said digit lines and a predetermined potential, and a plurality of field effect transistors arranged between said digit lines and said predetermined potential and in parallel with said resistive elements, the gates of said field effect transistors being supplied with said write end signal, in which effective resistance between said digit line and said predetermined potential is lowered in a transition period that the operation is shifted from a write operation to a read operation.

Claim 9

The memory device according to claim 5, wherein said control circuit includes a first inverter circuit for inverting said control signal, a second inverter circuit having an input supplied with and the inverted control signal from said first inverter circuit and a NOR gate having a first input terminal receiving an output of said first inverter circuit and a second input terminal receiving an output of said second inverter circuit.

Claim 10

The memory device according to claim 5, wherein the conducting resistance of said field effect transistor is smaller than the resistance of said resistive element.

Claim 11

The device of claim 5, said mode select circuit comprising first inverter means receiving an input from said control terminal, second inverter means receiving as an input the output of said first inverter means, third inverter means receiving as input the output of said first inverter means, wherein said write enable signal is provided by an output of said second inverter means, and said read enable signal is provided by an output of said third inverter means.

Claim 12

A static memory device in which a logic information to be written into a selected memory cell and a logic information readout from another selected memory cell are transferred through a digit line, comprising load means arranged between said digit lines and a predetermined potential and control means for making resistivity of said load means smaller in a transient period from a write cycle to a read cycle than it is in the write cycle and in the read cycle and in a transient period from a read cycle to a read cycle.

Claim 13

A static memory device in which a logic information to be written into a selected memory cell and a logic information readout from another selected memory cell are transferred through a digit line, comprising load means arranged between said digit lines and a predetermined potential and control means for making resistivity of said load means smaller in a transient period from a write cycle to a read cycle than it is in the write cycle and in the read cycle and in a transient period from a read cycle to a read cycle.

Claim 14

The memory device according to claim 9, further comprising detection means for detecting said transient period from a write cycle to a read cycle.

Claim 15

The memory device according to claim 9, further comprising means for supplying a control signal for selecting one of the write cycle and the read cycle.

Claim 16

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells, a plurality of load means arranged between said digit lines and a predetermined potential, said load means having controllable value of conductance, means for supplying a control signal having a first level for designating a write operation for writing data in said memory cells and a second level for designating a read operation for reading data from said memory cells, detection means for detecting a change in said control signal from said first level to said second level, said detection means generating an output signal of a third level over a predetermined period when said change is detected, and control means responsive to said third level signal for enhancing the conductance of said load means.

Claim 17

A memory device comprising a plurality of word lines, a plurality of digit lines, a plurality of memory cells, a plurality of load means arranged between said digit lines and a predetermined potential, said load means having controllable value of conductance, means for supplying a control signal having a first level for designating a write operation for writing data in said memory cells and a second level for designating a read operation for reading data from said memory cells, detection means for detecting a change in said control signal from said first level to said second level, said detection means generating an output signal of a third level over a predetermined period when said change is detected, and control means responsive to said third level signal for enhancing the conductance of said load means.

Claim 18

The memory device according to claim, 12 or 10 wherein said detection means comprises a series circuit of inverter means having an input terminal supplied with said control signal, a NOR gate means receiving an input from an early stage of said series circuit and another input from a later stage of said series circuits, the output of said NOR gate means providing output of said detection means.

Claim 19

The memory device according to claims 12 or 1, further comprising read means resposive to said second level of said control signal for sensing a read-out information on a selected digit line.

Claim 20

The memory device according to claim, 12 or 9 wherein said load means comprises a first field effect transistor being made normally conductive and a second field effect transistor being made conductive in response to said third level signal from said detection means.

Claim 21

The memory device according to claim, 12 or 9 wherein said detection means comprises a plurality of inverter circuits connected in series for delaying said control signal and a gate circuit receiving said control signal and the delayed control signal.

Claim 22

The memory device according to claims 12, 5, or 1, further comprising write means responsive to said first level of said control signal for supplying a selected digit line with a logic information to be written.

Claim 23

The memory device according to claims 12, 9 or 1, wherein said load means includes a first field effect transistor being made conductive and a second field effect transistor controlled by said control means.

Claim 24

The memory device according to claims 12, 9, 5, 3 or 1, wherein each of said memory cell includes a pair of cross-coupled transistors and a transfer gate transistor arranged between one of cross-coupled points and associated one of said digit lines.

Claim 25

The circuit according to claims 15, 5, 3 or 1, wherein a conductance of said second field effect transistor is larger than that of said first field effect transistor.

Claim 26

The circuit according to claims 12, 9, 5, 3 or 1 wherein said memory cell comprises a flip-flop circuit.