US5403729A
Expired / Lapsed
US
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Fabricating a semiconductor with an insulative coating
Assignee: CHIP SYSTEMS INNOVATIONS LLC
•
Filing: 1992-05-27
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Granted: 1995-04-04
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Expires: 2012-05-27
Abstract
Abstract An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry. The first metallic pad resides on the bottom of the right side portion. The first metallic pad provides a first polarity coupling to the integrated circuit. A method of fabricating the electrical apparatus is also described.
Inventors
- 👤 John G. Richards
- 👤 Hector Flores
- 👤 Wendell B. Sander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:32
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/099; H10P; H10P72/00; H10P72/70; H10P72/74; H10W44/00; H10W44/20; H10W72/00; H10W72/60; H10W90/00; H10P72/7438; H10W70/60; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
231 words
A method of fabricating an electrical apparatus, comprising the steps of: forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top; covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer; removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; and applying a first metal layer to a bottom of the first discrete region, wherein the first metal layer is physically separated from the second discrete region and does not physically contact the second discrete region.
Claim 2
Independent Claim
231 words
A method of fabricating an electrical apparatus, comprising the steps of: forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top; covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer; removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; and applying a first metal layer to a bottom of the first discrete region, wherein the first metal layer is physically separated from the second discrete region and does not physically contact the second discrete region.
Claim 3
Dependent Claim
19 words
The method of fabricating the electrical apparatus of claim 1, wherein the second insulating layer is an epoxy layer.
Claim 4
Dependent Claim
19 words
The method of fabricating the electrical apparatus of claim 1, wherein the second insulating layer is a plastic layer.
Claim 5
Dependent Claim
43 words
The method of fabricating the electrical apparatus of claim 1, wherein the applying step is performed prior to the step of covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with the second insulating layer.
Claim 6
Dependent Claim
42 words
The method of fabricating the electrical apparatus of claim 1, wherein the applying step is performed after the step of covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with the second insulating layer.
Claim 7
Dependent Claim
32 words
The method of fabricating the electrical apparatus of claim 1, wherein the applying step further comprising the step of applying the first metal layer to side surfaces of the first discrete region.
Claim 8
Dependent Claim
53 words
The method of fabricating the electrical apparatus of claim 1, wherein the applying step further comprises the step of applying a second metal to a bottom of the second discrete region, wherein the second metal layer is physically separated from the first discrete region and does not physically contact the first metal layer.
Claim 9
Dependent Claim
28 words
The method of fabricating the electrical apparatus of claim 1, further comprising the step of applying a third insulating layer on a bottom of the second discrete region.
Claim 10
Dependent Claim
44 words
The method of fabricating the electrical apparatus of claim 1, wherein the step of covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with the second insulating layer applies the second insulating layer by centrifugal force.
Claim 11
Independent Claim
239 words
A method of fabricating an electrical apparatus comprising the steps of: forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top: covering the integrated circuit with a first insulating layer: forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a first well at the contact point in the substrate such that the metallic interconnecting structure contacts a bottom of the first well to form the contact point; forming a second well in the substrate between the integrated circuit and the contact point, wherein the second well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate the metallic interconnecting structure, and the second well with a second insulating layer. wherein the metallic interconnecting structure is sandwiched by the second insulating layer: removing the semiconductor material residing below a bottom of the second well in to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit: applying a metal layer to a bottom Of the first discrete region.
Claim 12
Independent Claim
239 words
A method of fabricating an electrical apparatus comprising the steps of: forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top: covering the integrated circuit with a first insulating layer: forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a first well at the contact point in the substrate such that the metallic interconnecting structure contacts a bottom of the first well to form the contact point; forming a second well in the substrate between the integrated circuit and the contact point, wherein the second well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate the metallic interconnecting structure, and the second well with a second insulating layer. wherein the metallic interconnecting structure is sandwiched by the second insulating layer: removing the semiconductor material residing below a bottom of the second well in to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit: applying a metal layer to a bottom Of the first discrete region.
Claim 13
Independent Claim
268 words
A method of fabricating an electrical apparatus, comprising the steps of: forming an integrated Circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top: covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer: removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; applying a metal layer to a bottom of the first discrete region: and covering a portion of the metallic interconnecting structure, a portion of the top of the substrate with a rigid insulative layer before the step of forming the well, wherein the rigid insulative layer resides above the second discrete region, wherein the second insulating layer also covers the rigid insulative layer, wherein the second insulating layer is a flexible insulative layer.
Claim 14
Independent Claim
268 words
A method of fabricating an electrical apparatus, comprising the steps of: forming an integrated Circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top: covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer: removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; applying a metal layer to a bottom of the first discrete region: and covering a portion of the metallic interconnecting structure, a portion of the top of the substrate with a rigid insulative layer before the step of forming the well, wherein the rigid insulative layer resides above the second discrete region, wherein the second insulating layer also covers the rigid insulative layer, wherein the second insulating layer is a flexible insulative layer.
Claim 15
Independent Claim
226 words
A method of fabricating an electrical apparatus, comprising the steps of; forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top; covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer, wherein the second insulating layer comprises a first rigid insulative coating layer and a second flexible insulative coating layer; removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; applying a metal layer to a bottom of the first discrete region.
Claim 16
Independent Claim
226 words
A method of fabricating an electrical apparatus, comprising the steps of; forming an integrated circuit on a top of a substrate of a semiconductor material, wherein the integrated circuit includes a top; covering the integrated circuit with a first insulating layer; forming an opening through the first insulating layer to the top of the integrated circuit; forming a metallic interconnecting structure that electrically couples the top of the substrate to the top of the integrated circuit over the first insulating layer, wherein the metallic interconnecting structure contacts the top of the substrate at a contact point; forming a well in the substrate between the integrated circuit and the contact point, wherein the well resides below the metallic interconnecting structure; covering the first insulating layer, the top of the substrate, the metallic interconnecting structure, and the well with a second insulating layer, wherein the metallic interconnecting structure is sandwiched by the second insulating layer, wherein the second insulating layer comprises a first rigid insulative coating layer and a second flexible insulative coating layer; removing the semiconductor material residing below a bottom of the well in order to form a first discrete region of the semiconductor material that includes the contact point and a second discrete region of the semiconductor material that includes the integrated circuit; applying a metal layer to a bottom of the first discrete region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |