US3944447A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation
Assignee: International Business Machines Corp
•
Filing: 1973-03-12
•
Granted: 1976-03-16
•
Expires: 1993-03-12
Abstract
Abstract Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets. Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member.
Inventors
- 👤 Ingrid E. Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:13
CPC Classifications
H; H10; H10D; H10D86/00; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W20/00; H10W20/20; H10P90/1912; H10W10/011; H10W10/014; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/051; Y10S148/053; Y10S148/085; Y10S148/117; Y10S438/00; Y10S438/914; Y10S438/924; Y10S438/928
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
183 words
A method for fabricating an integrated circuit structure with full dielectric isolation comprising epitaxially depositing a layer of low conductivity silicon having a conductivity-determining impurity concentration <2 × 10 16 atoms/cm 3 on a silicon substrate having a conductivity-determining impurity concentration >3 × 10 18 atoms/cm 3 , forming an oxidation resistant protective layer over discrete spaced areas in said silicon layer, etching recesses in and thermally oxidizing the unprotected areas in said silicon layer to form silicon dioxide regions coextensive with and surrounding said spaced silicon areas and extending from said substrate through said silicon layer to the protected surface of said spaced silicon areas, forming a layer of dielectric material on said silicon layer, depositing a layer of polycrystalline silicon on said dielectric layer, removing said silicon substrate by preferential electrochemical anodic etching to provide spaced silicon pockets in said silicon layer, each respectively enclosed by silicon dioxide regions and said dielectric surface, and forming semiconductor devices in said pockets by the selective introduction of conductivity-determining impurities into the surface of said pockets exposed by the removal of said silicon substrate.
Claim 2
Independent Claim
183 words
A method for fabricating an integrated circuit structure with full dielectric isolation comprising epitaxially depositing a layer of low conductivity silicon having a conductivity-determining impurity concentration <2 × 10 16 atoms/cm 3 on a silicon substrate having a conductivity-determining impurity concentration >3 × 10 18 atoms/cm 3 , forming an oxidation resistant protective layer over discrete spaced areas in said silicon layer, etching recesses in and thermally oxidizing the unprotected areas in said silicon layer to form silicon dioxide regions coextensive with and surrounding said spaced silicon areas and extending from said substrate through said silicon layer to the protected surface of said spaced silicon areas, forming a layer of dielectric material on said silicon layer, depositing a layer of polycrystalline silicon on said dielectric layer, removing said silicon substrate by preferential electrochemical anodic etching to provide spaced silicon pockets in said silicon layer, each respectively enclosed by silicon dioxide regions and said dielectric surface, and forming semiconductor devices in said pockets by the selective introduction of conductivity-determining impurities into the surface of said pockets exposed by the removal of said silicon substrate.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said substrate in N type silicon.
Claim 4
Dependent Claim
21 words
The method of claim 2 wherein said layer of low conductivity silicon and said layer of polycrystalline silicon are epitaxially deposited.
Claim 5
Dependent Claim
89 words
The method of claim 3, wherein subsequent to the thermal oxidation and prior to forming said member on said low conductivity silicon layer, the protective layer is selectively removed from at least portions of some of said spaced areas abutting said silicon dioxide regions, and conductivity-determining impurities are selectively introduced into the exposed portions to form regions of selected conductivity defined by said abutting silicon dioxide regions and the remaining protective layer, said regions of selected conductivity becoming buried regions when said member is formed on said silicon layer.
Claim 6
Dependent Claim
12 words
The method of claim 4 wherein said protective layer is silicon nitride.
Claim 7
Dependent Claim
12 words
The method of claim 2 wherein said protective layer is silicon nitride.
Claim 8
Dependent Claim
88 words
The method of claim 4 wherein, in the formation of semiconductor devices by said selective introduction of inpurities, a layer of dielectric material is formed on the surface exposed by the removal of said substrate, and openings are formed in said dielectric layer to provide a mask, and conductivity-determining impurities are introduced through said openings to form regions of selected conductivity in the substrate, some of said openings abutting the silicon dioxide regions surrounding said silicon pockets whereby the regions formed are defined by said silicon dioxide regions.
Claim 9
Dependent Claim
54 words
The method of claim 7, wherein the steps of introduction of conductivity-determining impurities into the surface covered by said protective layer and into the surface covered by said masks are carried out so that in at least one pocket in said silicon layer, the surrounding silicon dioxide defines regions being formed at both surfaces.
Claim 10
Dependent Claim
65 words
The method of claim 7, further including the steps of forming a layer of dielectric material over the surface of said pockets into which impurities have been diffused in the formation of semiconductor devices, and forming openings in said dielectric layer, some of which openings abut the silicon dioxide regions surrounding said pockets, and depositing metal in said openings to provide contacts to said devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-16 | 1979-09-15 | 1980-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-16 | 1983-09-15 | 1984-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-16 | 1987-09-15 | 1988-03-16 | $7700.00 | Window Closed / Lapsed |