US5353436A
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Method and apparatus for synchronizing a plurality of processors
Assignee: Tandem Computers Inc
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Filing: 1992-12-09
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Granted: 1994-10-04
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Expires: 2012-12-09
Abstract
Abstract A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow of the event counter forces resynchronization. A cycle counter is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.
Inventors
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/184; G06F11/1658; G06F11/1666; G06F11/1675; G06F11/1683; G06F11/1687; G06F11/1691; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F11/1679; G06F11/185; G06F11/20; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
An apparatus for synchronizing a plurality of processors, each of said processors executing an instruction stream at varying speeds in accordance with respective independent clock cycles, comprising: event indicating means for detecting prescribed events within each processor and providing an indication thereof; event counting means, connected to the event indicating means, for counting the number of events indicated for each processor; clock cycle counting means for separately counting the clock cycles of each processor and for issuing a synchronization request upon reaching a predetermined count value for any processor; means for detecting extra clock cycles, not normally present during execution of the instruction, while the clock cycle counting means is counting and preventing said clock cycle counting means from counting said extra clock cycles; and suspension means, connected to the event counting means, the clock cycle counting means and to each processor, for receiving said synchronization request and for suspending processing of a processor when the number of events counted for that processor is greater than the number of events for another processor.
Claim 2
Independent Claim
173 words
An apparatus for synchronizing a plurality of processors, each of said processors executing an instruction stream at varying speeds in accordance with respective independent clock cycles, comprising: event indicating means for detecting prescribed events within each processor and providing an indication thereof; event counting means, connected to the event indicating means, for counting the number of events indicated for each processor; clock cycle counting means for separately counting the clock cycles of each processor and for issuing a synchronization request upon reaching a predetermined count value for any processor; means for detecting extra clock cycles, not normally present during execution of the instruction, while the clock cycle counting means is counting and preventing said clock cycle counting means from counting said extra clock cycles; and suspension means, connected to the event counting means, the clock cycle counting means and to each processor, for receiving said synchronization request and for suspending processing of a processor when the number of events counted for that processor is greater than the number of events for another processor.
Claim 3
Dependent Claim
59 words
The apparatus according to claim 1 further comprising sync request means, connected to the suspension means, for receiving a synchronization request signal, wherein the suspension means suspends processing of a processor in response to the synchronization request signal when the number of events counted for that processor is not less than the number of events counted for another processor.
Claim 4
Dependent Claim
35 words
The apparatus according to claim 2 further comprising restart means, connected to the suspension means and to each processor, for restarting a suspended processor when the number of events counted for each processor is equal.
Claim 5
Dependent Claim
37 words
The apparatus according to claim 3 wherein the suspension means suspends processing of a processor when the number of events counted for that processor is not less than the number of events counted for a suspended processor.
Claim 6
Dependent Claim
219 words
In a multiple processor system wherein each processor executes a program having a plurality of events defined therein, the plurality of events occurring in the same order in each processor but at varying times, a method of synchronizing each processor with the other processors comprising the steps of, for each processor: detecting prescribed events; counting the number of said detected events; counting the number of clock cycles occurring after an event is detected; detecting, during said clock cycle counting step, extra clock cycles not normally present during execution of the instruction; inhibiting the clock cycle counting step during the extra clock cycles; providing a synchronization request signal when the number of events counted equals a first prescribed value or when the number of counted clock cycles reaches a second prescribed value; suspending processing of the processor when the next event following said synchronization request signal is detected; comparing the number of events counted with the number of events counted by the other processors; continuing processing when the number of events counted for the processor is less than the number of events counted for another processor; suspending processing when the number of events counted is equal to the maximum number of events counted by any processor; and continuing processing when the number of events counted for each processor is equal.
Claim 7
Dependent Claim
219 words
In a multiple processor system wherein each processor executes a program having a plurality of events defined therein, the plurality of events occurring in the same order in each processor but at varying times, a method of synchronizing each processor with the other processors comprising the steps of, for each processor: detecting prescribed events; counting the number of said detected events; counting the number of clock cycles occurring after an event is detected; detecting, during said clock cycle counting step, extra clock cycles not normally present during execution of the instruction; inhibiting the clock cycle counting step during the extra clock cycles; providing a synchronization request signal when the number of events counted equals a first prescribed value or when the number of counted clock cycles reaches a second prescribed value; suspending processing of the processor when the next event following said synchronization request signal is detected; comparing the number of events counted with the number of events counted by the other processors; continuing processing when the number of events counted for the processor is less than the number of events counted for another processor; suspending processing when the number of events counted is equal to the maximum number of events counted by any processor; and continuing processing when the number of events counted for each processor is equal.
Claim 8
Dependent Claim
22 words
A method as set out in claim 5, wherein said step of detecting extra clock cycles comprises detecting a processor cache miss.
Claim 9
Dependent Claim
21 words
A method as set out in claim 5, wherein said step of detecting extra clock cycles comprises detecting a processor retry.
Claim 10
Dependent Claim
21 words
A method as set out in claim 7, wherein said step of detecting extra clock cycles comprises detecting a parity error.
Claim 11
Dependent Claim
32 words
A method as set out in claim 8, wherein said step of detecting extra clock cycles comprises detecting execution or an error routine by said processor in response to said parity error.
Claim 12
Dependent Claim
36 words
A method as set out in claim 5, wherein said step of detecting extra clock cycles comprises detecting execution of different code in one or more of said processors, said different code requiring extra clock cycles.
Claim 13
Dependent Claim
24 words
A method as set out in claim 5, wherein said step of detecting extra clock cycles comprises detecting clock cycles associated with asynchronous logic.
Claim 14
Dependent Claim
241 words
A computer system comprising: a plurality of processors, each for processing in accordance with independent clock cycles such that said processing may be asynchronous between processors over plural clock cycles; and a plurality of synchronizing means, respectively corresponding to said plurality of processors, each said synchronizing means comprising: event indicating means for detecting a prescribed event within the corresponding processor and providing an indication thereof; event counting means, connected to the event indicating means, for counting the number of events indicated; comparison means, connected to the event counting means of each processor, for providing a signal when the number of events counted for the corresponding processor is greater than the number of events counted for another processor; cycle counter means for counting the number of clock cycles occurring after an event; means for providing a synchronization request signal to the processor when the number of events counted equals a first prescribed value or when the number of clock cycles counted equals a second prescribed value; extra clock indicating means for indicating when the processor uses extra clock cycles to execute a program; and synchronization means for suspending processing of the corresponding processor in response to said synchronization request signal when the number of events counted for the processor is not less than the number of events counted for another processor, said synchronization means providing a restart signal to the processor when the number of events counted for each processor is equal.
Claim 15
Dependent Claim
241 words
A computer system comprising: a plurality of processors, each for processing in accordance with independent clock cycles such that said processing may be asynchronous between processors over plural clock cycles; and a plurality of synchronizing means, respectively corresponding to said plurality of processors, each said synchronizing means comprising: event indicating means for detecting a prescribed event within the corresponding processor and providing an indication thereof; event counting means, connected to the event indicating means, for counting the number of events indicated; comparison means, connected to the event counting means of each processor, for providing a signal when the number of events counted for the corresponding processor is greater than the number of events counted for another processor; cycle counter means for counting the number of clock cycles occurring after an event; means for providing a synchronization request signal to the processor when the number of events counted equals a first prescribed value or when the number of clock cycles counted equals a second prescribed value; extra clock indicating means for indicating when the processor uses extra clock cycles to execute a program; and synchronization means for suspending processing of the corresponding processor in response to said synchronization request signal when the number of events counted for the processor is not less than the number of events counted for another processor, said synchronization means providing a restart signal to the processor when the number of events counted for each processor is equal.
Claim 16
Dependent Claim
126 words
A computer system comprising: a plurality of processors, each processing in accordance with independent clock cycles such that said processing may be asynchronous over plural clock cycles; and a plurality of synchronizing circuits, respectively corresponding to said plurality of processors, each comprising: cycle counter means for counting the number of clock cycles of the corresponding processor; extra clock cycle detecting means for detecting when the processor uses extra clock cycles to execute a program and preventing said cycle counter means from counting said extra cycles; means for providing a synchronizing request signal to the processors when the number of clock cycles counted equals a prescribed value; and synchronization means for synchronizing the processors at the same clock cycle count in response to said synchronization request signal.
Claim 17
Dependent Claim
126 words
A computer system comprising: a plurality of processors, each processing in accordance with independent clock cycles such that said processing may be asynchronous over plural clock cycles; and a plurality of synchronizing circuits, respectively corresponding to said plurality of processors, each comprising: cycle counter means for counting the number of clock cycles of the corresponding processor; extra clock cycle detecting means for detecting when the processor uses extra clock cycles to execute a program and preventing said cycle counter means from counting said extra cycles; means for providing a synchronizing request signal to the processors when the number of clock cycles counted equals a prescribed value; and synchronization means for synchronizing the processors at the same clock cycle count in response to said synchronization request signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |