Fault tolerant computational system and voter circuit

Claim 2

A fault-tolerant computation system comprising: a plurality of computational devices producing binary data output signals; and a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computation devices; wherein: each computational device receives the output from the voter circuit and each of the other computational devices, whereby a disagreement between the voter circuit and one of the computational devices may be detected.

Claim 3

A fault-tolerant computational system comprising: a plurality of computational devices producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; and a fault detection device for receiving the outputs from the voter circuit and each of the computational devices whereby a disagreement between the voter circuit and one of the computational devices may be detected.

Claim 4

A fault-tolerant computational system comprising: a plurality of computational devices producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; and a fault detection device for receiving the outputs from the voter circuit and each of the computational devices whereby a disagreement between the voter circuit and one of the computational devices may be detected.

Claim 5

The fault-tolerant computational system of claims 1 or 2 adapted for three computational devices, wherein: the voter circuit includes three pairs of electronic control valves with each of said control valves within each pair connected in series, and the three pairs connected in parallel, and each of said electronic control valves connected to receive an input from one of the computational devices such that each of said pairs of electronic control valves receives a different combination of inputs from the computational devices, and including a resistive network connected to the three pairs of electronic control valves.

Claim 6

The fault-tolerant computational system of claims 3, 1 or 2, wherein: the computational devices produce clock pulses; and further comprising: a clock circuit connected to each of the computational devices for receiving said clock pulses, the output of the clock circuit being connected to each of the computational devices for synchronizing the output data of the computational devices fed to the voter circuit.

Claim 7

The fault-tolerant computational system of claim 4, wherein: the clock circuit includes a plurality of pulse counters with each of said counters connected to receive said clock pulses from one of the computational devices, and a voter circuit included in the clock circuit which receives an output from each of said counters and provides an output fed back to each of the counters and fed to each of the computational devices whereby said output resets each of said counters and synchronizes the data output from the computational devices.

Claim 8

A fault-tolerant computational system comprising: a plurality of computational devices producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; and a clock circuit connected to each of the computational devices for receiving said clock pulses, the output of the clock circuit being connected to each of the computational devices for synchronizing the output of data of the computational devices fed to the voter circuit; the voter circuit including sets of electronic control valves with each of said control valves within each set connected in series, and the sets connected in parallel, and each of said electronic control valves connected to receive the input from one of the computational devices such that each of said sets of electronic control valves receives a different combination of inputs from the computational devices, and including a resistive network connected to the sets of electronic control valves; the clock circuit including a plurality of pulse counters with each of said counters connected to receive said clock pulse from one of the computational devices, and a voter circuit included in the clock circuit to receive an output from each of said counters and provide an output fed back to each of the counters and fed to each of the computational devices whereby said output can reset each of said counters and synchronize the data output from the computational devices; and each computational device connected to receive the output from the voter circuit and each of the other computational devices whereby a disagreement between the voter circuit and one of the computational devices may be detected.

Claim 9

A fault-tolerant computational system comprising: a plurality of computational devices producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; and a clock circuit connected to each of the computational devices for receiving said clock pulses, the output of the clock circuit being connected to each of the computational devices for synchronizing the output of data of the computational devices fed to the voter circuit; the voter circuit including sets of electronic control valves with each of said control valves within each set connected in series, and the sets connected in parallel, and each of said electronic control valves connected to receive the input from one of the computational devices such that each of said sets of electronic control valves receives a different combination of inputs from the computational devices, and including a resistive network connected to the sets of electronic control valves; the clock circuit including a plurality of pulse counters with each of said counters connected to receive said clock pulse from one of the computational devices, and a voter circuit included in the clock circuit to receive an output from each of said counters and provide an output fed back to each of the counters and fed to each of the computational devices whereby said output can reset each of said counters and synchronize the data output from the computational devices; and each computational device connected to receive the output from the voter circuit and each of the other computational devices whereby a disagreement between the voter circuit and one of the computational devices may be detected.

Claim 10

A fault-tolerant computational system comprising: a set of three computational devices to produce binary data output signals; and a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; the voter circuit including three pairs of electronic control valves with the two electronic control valves in each pair connected in series, and the three said pairs connected in parallel, and each of said control valves connected to receive an input from one of the computational devices such that each of said pairs of electronic control valves can receive a different combination of two inputs from differing respective pairing of the three computational devices, and in a manner such that no two electronic control valves which constitute such a pair have their respective inputs connected to the same computational device, and including a resistive network connected to the three pairs of electronic control valves; whereby whenever at least two of the computational devices produce an identical output, one of the pairs of electronic valves will have the two valves in that pair connected to the respective outputs of the two computational devices producing identical outputs, and thereby cause the two electronic valves in said pair to attain the same state as to being either on or off, and thus result in an output voltage across the resistor network corresponding to the state of said electronic valves.

Claim 11

A fault-tolerant computational system comprising: a set of three computational devices to produce binary data output signals; and a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with a majority of the binary input data signals received from the computational devices; the voter circuit including three pairs of electronic control valves with the two electronic control valves in each pair connected in series, and the three said pairs connected in parallel, and each of said control valves connected to receive an input from one of the computational devices such that each of said pairs of electronic control valves can receive a different combination of two inputs from differing respective pairing of the three computational devices, and in a manner such that no two electronic control valves which constitute such a pair have their respective inputs connected to the same computational device, and including a resistive network connected to the three pairs of electronic control valves; whereby whenever at least two of the computational devices produce an identical output, one of the pairs of electronic valves will have the two valves in that pair connected to the respective outputs of the two computational devices producing identical outputs, and thereby cause the two electronic valves in said pair to attain the same state as to being either on or off, and thus result in an output voltage across the resistor network corresponding to the state of said electronic valves.

Claim 12

A fault-tolerant computational system comprising: a plurality of computational devices for producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with the majority of the binary input data signals received from the computational devices; and a clock circuit connected to each of the computational devices for receiving said clock pulses, the output of the clock circuit being connected to each of the computational devices for synchronizing the output of data of the computational devices fed to the voter circuit; the clock circuit including a plurality of pulse counters with each of said counters connected to receive said clock pulses from one of the computational devices, and a second voter circuit, included in the clock circuit, to receive an output from each of said counters and provide an output fed back to each of the counters and fed to each of the computational devices whereby said output of the voter circuit can reset each of said counters and synchronize the data output from the computational devices.

Claim 13

A fault-tolerant computational system comprising: a plurality of computational devices for producing binary data output signals and clock pulses; a voter circuit having an input connected to each of the computational devices to receive the data output signals of the devices and adapted for producing an output which agrees with the majority of the binary input data signals received from the computational devices; and a clock circuit connected to each of the computational devices for receiving said clock pulses, the output of the clock circuit being connected to each of the computational devices for synchronizing the output of data of the computational devices fed to the voter circuit; the clock circuit including a plurality of pulse counters with each of said counters connected to receive said clock pulses from one of the computational devices, and a second voter circuit, included in the clock circuit, to receive an output from each of said counters and provide an output fed back to each of the counters and fed to each of the computational devices whereby said output of the voter circuit can reset each of said counters and synchronize the data output from the computational devices.