US3921149A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer comprising three data processors
Assignee: Hasler AG
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Filing: 1974-03-26
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Granted: 1975-11-18
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Expires: 1994-03-26
Abstract
Abstract Circuitry for enabling three processors having no common circuit to operate in parallel in a computer, to be synchronized with one another after the execution of every instruction and after every access to a common memory. The operation of the system is not impaired by a failure in one of the three processors, but the faulty processor is rendered inactive and a failure indication is given.
Inventors
- 👤 Werner Kreis
- 👤 Peter Laderach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/181; G06F1/00; G06F1/04; G06F1/12; G06F11/183; G06F11/184
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
183 words
A computer comprising a memory and three data processors connected to said memory and simultaneously executing identical instructions, each of said processors including a clock, a calculating unit, a control unit connected to receive clock pulses from said clock and connected to control said calculating unit, and synchronizing means connected to said three data processors for synchronizing the respective processor with the two other processors at the end of the execution of each instruction, each synchronizing means including a. pulse generating means having an output delivering a first pulse at the end of the execution of each of said instructions, b. a majority gate having three inputs each connected to the output of said pulse generating means of said control unit of one of said data processors, and having an output delivering a second pulse on the simultaneous receipt of one of said first pulses on at least two of said three inputs of said majority gate, and c. starting means connected to said output of said majority gate and starting the execution of the following instruction on reception of said second pulse.
Claim 2
Dependent Claim
183 words
A computer comprising a memory and three data processors connected to said memory and simultaneously executing identical instructions, each of said processors including a clock, a calculating unit, a control unit connected to receive clock pulses from said clock and connected to control said calculating unit, and synchronizing means connected to said three data processors for synchronizing the respective processor with the two other processors at the end of the execution of each instruction, each synchronizing means including a. pulse generating means having an output delivering a first pulse at the end of the execution of each of said instructions, b. a majority gate having three inputs each connected to the output of said pulse generating means of said control unit of one of said data processors, and having an output delivering a second pulse on the simultaneous receipt of one of said first pulses on at least two of said three inputs of said majority gate, and c. starting means connected to said output of said majority gate and starting the execution of the following instruction on reception of said second pulse.
Claim 3
Dependent Claim
37 words
A computer as set forth in claim 1, wherein each of said synchronizing means further includes delay means connected in series with said majority gate between said output of said pulse generating means and said starting means.
Claim 4
Dependent Claim
170 words
A computer comprising at least one memory having an access control input, and ''''end of access'''' output and a data output, a majority gating means for each memory, each of said majority gating means having three inputs and an output which is connected to said access control input of the respective memory, three data processors, each including a. a control unit having an input and an access request output delivering a memory access request signal on a signal on said control unit input and connected to one of said inputs of said majority gating means, b. synchronizing means connected to said three data processors for synchronizing the respective data processor with the said other two data processors on every one of said access request signals, and including a flip-flop circuit having a set input connected to said ''''end of access'''' output of said memory, a reset input connected to said access request output of the respective control unit and a set output connected to said input of said control unit.
Claim 5
Dependent Claim
170 words
A computer comprising at least one memory having an access control input, and ''''end of access'''' output and a data output, a majority gating means for each memory, each of said majority gating means having three inputs and an output which is connected to said access control input of the respective memory, three data processors, each including a. a control unit having an input and an access request output delivering a memory access request signal on a signal on said control unit input and connected to one of said inputs of said majority gating means, b. synchronizing means connected to said three data processors for synchronizing the respective data processor with the said other two data processors on every one of said access request signals, and including a flip-flop circuit having a set input connected to said ''''end of access'''' output of said memory, a reset input connected to said access request output of the respective control unit and a set output connected to said input of said control unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-17 | 1979-05-19 | 1979-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-17 | 1983-05-19 | 1983-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-17 | 1987-05-19 | 1987-11-18 | $7700.00 | Window Closed / Lapsed |