Data processing arrangements having convertible majority decision voting

Claim 2

In a data processing arrangement, in combination: a processing unit; a plurality of data means for producing data signal outputs to be processed by said processing unit; a majority decision gating circuit having a plurality of inputs connected to the data signal outputs of said data means and an output connected to said processing unit for conveying a majority decision signal to the processing unit so as to secure against a minority dissenting vote; and control means connected to said majority decision gating circuit for selectively converting it to a simple gate in which its output signal is solely dependent upon a predetermined one of said data signal outputs.

Claim 3

In a data processing arrangement as defined in claim 1 wherein said majority decision gating circuit comprises a bank of NAND gates each receiving a different combination of the majority of said data signal outputs, and a further NAND gate receiving the outputs of said bank of NAND gates; and wherein said control means comprises an inverter having a control signal input and an output connected to all NAND gates of said bank, and a control NAND gate having said control signal input and an input from said one data signal output and having an output connected to said further NAND gate.

Claim 4

In a data processing arrangement, in combination: three first units, three majority decision gating circuits, and three second units, each of said first units having an input connected to an output of a respective one of said majority decision gating circuits and each of said majority decision gating circuits receiving an input from each of said second units; and control means connected to at least one of said majority decision gating circuits for converting it to a simple gate in which its output is dependent solely upon the input from a predetermined one of said second units, whereby said one second unit and that first unit associated with said one majority decision gating circuit may be isolated for testing purposes while the remaining portion oF the arrangement continues to operate the basis of majority decision.

Claim 5

In a data processing arrangement, in combination: three first units, three majority decision gating circuits, and three second units, each of said first units having an input connected to an output of a respective one of said majority decision gating circuits and each of said majority decision gating circuits receiving an input from each of said second units; and control means connected to at least one of said majority decision gating circuits for converting it to a simple gate in which its output is dependent solely upon the input from a predetermined one of said second units, whereby said one second unit and that first unit associated with said one majority decision gating circuit may be isolated for testing purposes while the remaining portion oF the arrangement continues to operate the basis of majority decision.

Claim 6

In a data processing arrangement as defined in claim 3 wherein each majority decision gating circuit comprises three NAND gates each having a pair of inputs from a different combination of outputs from said second units, and a further NAND gate having inputs from said three NAND gates; and wherein said control means comprises an inverter having a control signal and an output connected to each of said three NAND gates, and a control NAND gate having said control signal input and an input from said one second unit, and having an output connected to said further NAND gate.

Claim 7

In a data processing system, the combination of: at least three data processing loops, each loop comprising a plurality of components and each component having input means and output means; majority voting circuit means providing the input means for each of said components and the output means of like components of all the loops being connected to the majority voting circuit means of like other components of all of the loops whereby normally to operate the system on the basis of majority voting indiscriminately within the totality of components of the system; control means for isolating each loop to function independently of the remaining portion of the system while such remaining portion of the system continues to operate on the basis of majority voting, said control means comprising plural control signal means, one for each loop, and each connected to all the majority voting circuit means belonging to its associated loop for selectively passing only those output signals belonging to the components of said associated loop, whereby an isolated loop may be tested independently and without disturbing the remaining portion of the system.

Claim 8

In a data processing system, the combination of: at least three data processing loops, each loop comprising a plurality of components and each component having input means and output means; majority voting circuit means providing the input means for each of said components and the output means of like components of all the loops being connected to the majority voting circuit means of like other components of all of the loops whereby normally to operate the system on the basis of majority voting indiscriminately within the totality of components of the system; control means for isolating each loop to function independently of the remaining portion of the system while such remaining portion of the system continues to operate on the basis of majority voting, said control means comprising plural control signal means, one for each loop, and each connected to all the majority voting circuit means belonging to its associated loop for selectively passing only those output signals belonging to the components of said associated loop, whereby an isolated loop may be tested independently and without disturbing the remaining portion of the system.

Claim 9

In a data processing system as defined in claim 5 wherein each loop comprises three components, a central processing unit, a data store and a program store; the output means of all central processing units being connected to all majority voting circuit means belonging to all of said data stores and all of said program stores; each central processing unit having two majority voting circuit means associated therewith; the output means of all said data stores being connected to one majority voting circuit means of each control processing unit; and the output means of all said program stores being connected to the other majority voting circuit means of each central processing unit.