EP0286856B1
Expired / Lapsed
EP
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Fault-tolerant computer arrangement
Assignee: BBC Brown Boveri AG Switzerland
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Filing: 1988-03-16
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Granted: 1993-05-19
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Expires: 2008-03-16
Abstract
Abstract This arrangement is based on the duplex concurrence principle with two closely coupled but spatially separable computers of identical construction and loaded with corresponding programmes and connectable to common or redundant input channels and to a common output channel. The two computers are multiprocessors. A device is described which synchronises the two identical computers so closely that both computers execute their programmes in step with the clock. In addition, the device allows the input data and the interrupts to be matched, an empty processor to be trained after it has been repaired and various functions for acquiring and dropping synchronisation in non-deterministic operations. The device utilises special properties of the buses of the two multiprocessors, which are also described. <IMAGE>
Inventors
- 👤 Hubert Dr. Kirrmann
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 05:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1641; G06F11/1645; G06F11/1658; G06F11/1675; G06F11/1679; G06F11/20; G06F11/2097
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
266 words
Fault-tolerant computer arrangement, based on the duplex concurrent principle with two closely linked, but spatially separable, identically constructed computers (L, R) which are loaded with matching programs and can be connected to common or redundant input channels and to a common output channel, characterised by the following features: - in both computers (L, R) a plurality of processors (P) are connected, besides to a common input and output device (EA.c) and a common memory (M.c), to a common bus (B.c) in each case; - the common bus (B.c) has the ability of notifying each information item which it transfers, such as address or read and write data, also to processors (P) other than the actual addressees; - a synchronisation unit (USU) connected to the buses (B.c) of both computers (L, R) is provided, which has two identical halves, each of which is connected to one of the common buses (B.c) and which are connected to one another via a communications channel; - the synchronisation unit (USU) synchronises the two computers (L, R) without directly influencing the individual processors (P) in that it generates signals (RP*, BW* and BB*) in each of its two halves which serve to extend (signal RP*) each cycle in the buses (B.c) connected to the two halves of the synchronisation unit (USU) as desired, and to start a bus arbitration again whenever the two computers (L, R) are assigned (BW*, BB*) to different processors (P) acting as bus masters; - the communications channel permits the transmission of data, addresses and control signals from one common bus to the other and vice versa.
Claim 2
Dependent Claim
94 words
Computer arrangement according to Claim 1, characterised by the following features: - the communications channel has two unidirectional subchannels for the bidirectional transmission of data, addresses and control signals; - a comparator which is connected in each case to the two subchannels is provided in the two halves of the synchronisation unit; - buffers (1, 2, ..., 8) are provided in the two subchannels, via which buffers the data, addresses and control signals of a common bus (B.c) can be switched through selectively to the comparators or to the respective other bus when required.
Claim 3
Dependent Claim
115 words
Computer arrangement according to Claim 2, characterised by the following features: - a local controller and a remote controller are provided in each half of the synchronisation unit (USU); - the local controller of each half of the synchronisation unit handles in each case the control of processes on the common bus to which the respective half is connected; - the remote controller serves to transmit the status of the half of the synchronisation unit to which it is assigned to the respective other half; - the possible statuses of the two halves of the synchronisation unit are derived from the statuses of a plurality of registers provided in the two halves in each case.
Claim 4
Dependent Claim
99 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - all the data transmitted via the buses (B.c) from all units connected to them, such as the processors (P), the input and output device (EA.c) and the memory (M.c), can be received in both computers (L, R); - the duration of the bus cycles is determined in both computers (L, R) by the slowest participating unit in each case; - the synchronisation unit (USU) delays each bus cycle until the same bus cycle also occurs on the bus of the respective other computer.
Claim 5
Dependent Claim
128 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - the access authorisation to the common bus (B.c) is determined by an arbitration procedure; - the identity of the respective winner of an arbitration procedure is transmitted via lines of the common bus (B.c) in each case; - the respective winner can be discontinued within a specifiable time span after arbitration has ended, and a repeat of the arbitration procedure can be forced; - the synchronisation unit (USU) compares in each case the identity of the winners of parallel arbitrations on the buses (B.c) of the two computers (L, R) and again discontinues these in each case and again forces a new arbitration in each case if their identity is not identical.
Claim 6
Dependent Claim
103 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - for at least one unit, designed as input device (EA.c), in each of the computers there is a corresponding unit, likewise designed as input device (EA.c), in the respective other computer, but with a different address; - if one of two mutually corresponding input devices (EA.c) is simultaneously addressed in the two computers (L, R), then the synchronisation unit (USU) transfers the data supplied by the aforesaid input device (EA.c) on the bus (B.c) to which it is connected across to the bus of the other computer.
Claim 7
Dependent Claim
256 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - the processors (P) can be interrupted by an interrupt request; - there is present in each processor (P) an interrupt unit (ZZ, UR) which has a cycle selector (ZZ) and an interrupt register (UR) that can be read from the common bus (B.c) in each case; - the processors (P) recognize only interrupt requests generated by their associated cycle selectors (ZZ); - all other interrupt requests do not lead directly to an interrupt, but rather are stored in the interrupt register (UR) in each case; - the interrupt registers (UR) of mutually corresponding processors (P) in the two computers (L, R) have a different address; - the cycle counters (ZZ) interrupt their associated processors (P) in each case after a predetermined number of cycles in each case; - the interrupted processors (P) read the contents of their associated interrupt registers (UR) via the common bus (B.c), to which they are connected in each case, and also in addition read the contents of the interrupt registers (UR) of the respective processors (P) corresponding to them in the other computer via the common bus of the respective other computer; - to permit the last-mentioned read operation, the synchronisation unit (USU) connects the common buses (B.c) of the two computers (L, R) to one another for the duration of the read operation; - read, mutually corresponding interrupt requests are aligned with one another in the two computers (L, R) in the same way.
Claim 8
Dependent Claim
191 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - if one computer (pupil) has failed and if it is to be put into operation again, the respective corresponding processors in the two computers are set in pairs to the same program address; - the failed computer (pupil) is set to a learning mode and the non-failed computer is set to a teaching mode; - the I/O devices (EA.c, EA.p) and the memories (M.I; M.c, M.p) of a computer in the learning mode ignore all learn requests; - the data appearing as a result of the read requests on the common bus (B.c) of the computer (teacher) in the teaching mode are transferred by the synchronisation unit (USU) across to the common bus (B.c) of the computer in the learning mode; - the computer in the teaching mode gradually reads all address items of its memories via its common bus parallel to the execution of its normal program; - the synchronisation unit transfers the data across to the bus of the computer in the learning mode also in the case of the last-mentioned read operations.
Claim 9
Dependent Claim
233 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - all the data transmitted over the buses (B.c) from all units connected to them, such as processors (P), input and output device (EA.c) and memory (M.c), can be received in both computers (L, R); - the duration of the bus cycles is determined in both computers (L, R) by the slowest participating unit in each case; - the synchronisation unit (USU) delays each bus cycle until the same bus cycle also occurs on the bus of the respective other computer; - two mutually corresponding processors (P) in the two computers (L, R) which wish to execute non-deterministic operations notify the synchronisation unit (USU) of this; - after these messages have been received, the synchronisation unit (USU) does not synchronise the bus cycles of the aforesaid processors (P); - as soon as one of the two aforesaid, no longer synchronised, processors is ready to be resynchronised, it signals this to the synchronisation unit and goes into a wait loop until the corresponding processor in the other computer also signals its readiness for resynchronisation and likewise goes into a wait loop; - when the aforesaid processors are ready for resynchronisation in this way, the synchronisation unit sends them an interrupt request simultaneously, in each case causing the processors to exit their wait loops and to continue resynchronised as normal.
Claim 10
Dependent Claim
94 words
Computer arrangement according to one of Claims 1 - 3, characterised by the following features: - if only one of the computers (L) is working, while the other (R) is waiting for the completion of the work, the common memory (M.c) of the waiting computer (R) is updated by the synchronisation unit (USU) in that the synchronisation unit (USU) transfers the data that are written via the bus (B.c) of the working computer (L) into the common memory (M.c) of the working computer (L) across to the bus (B.c) of the waiting computer (R).
References Cited (Backward Citations)
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