Plurality of processors where access to the common memory requires only a single clock interval

Claim 1

A multi-microprocessor apparatus comprising in combination: a plurality of central processing units to receive and process data signals, said plurality of central processing units arranged in parallel with one another, each of said plurality of central processing units respectively including a means for synchronizing which is operatively connected thereto to synchronize the flow of data and signals through each central processing unit, said synchronizing means synchronizing each of said central processing units to a common clock reference, a plurality of local memory units respectively connected to said plurality of central processing units, each of said plurality of local memory units storing data, instruction and control signals, each central processing unit of said plurality of central processing units communicating only with its local memory unit of said plurality of local memory units, and, a means for a common memory coupled directly to each of said plurality of central processing units, said common memory means providing data, instruction and control signals to each central processing unit of said plurality of central processing units, the communications between each of said plurality of central processing units and said common memory means being synchronized by its respective synchronizing means wherein access thereto requires only a single clock interval.