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US3761884A
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Arrangement for synchronizing a number of co-operating computers
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1971-11-04
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Granted: 1973-09-25
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Expires: 1991-11-04
Abstract
Abstract A synchronizing apparatus in a data system comprising a number of individual computers each of which includes a binary counter. The synchronization implies that a predetermined value should be stored in certain positions in counters in all the computers. A synchronizing signal is sent on a common line interconnecting all the computers from the computer which operates more rapidly than the other computers of the system and when reaching the predetermined value in the associated counter, this signal being fed is all the other counters in order to set these counters to such predetermined value.
Inventors
- 👤 O Avsan
- 👤 A Grodal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4282; G06F13/4291; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
275 words
In a digital computer system comprising a number of computers, each including an n-digit binary counter which is incremented by stepping pulses generated by a clock circuit where said counter when reaching a predetermined count position determines an interval at the beginning of which each computer shall return to a specific point in a program, each computer including an arrangement for synchronizing said counter by setting certain of said n digits of the counter to a predetermined binary value by means of a set pulse, and means for producing a synchronizing signal when said counter reaches a predetermined position, and each computer being connected to a common bus line to enable the synchronizing signal produced in one of said computers to be transferred to all of the computers, said arrangement comprising: a blocking logic circuit including a bistable circuit, having a set input, reset input and an output, said bistable circuit being triggered to a set state upon receipt of a signal at said set input and being triggered to a reset state upon receipt of a signal at said reset input; means for transmitting said synchronizing signal to said set input; a pulse generating circuit having an input connected to said bistable circuit and an output for delivering said set pulse to said counter when said bistable circuit is set by said synchronizing signal; and locking means for connecting the output of said pulse generating circuit to said reset input of said bistable circuit in order for said bistable circuit to be reset by said set pulse, whereby said bistable circuit is locked in the reset state as long as said set pulse prevails.
Claim 2
Dependent Claim
275 words
In a digital computer system comprising a number of computers, each including an n-digit binary counter which is incremented by stepping pulses generated by a clock circuit where said counter when reaching a predetermined count position determines an interval at the beginning of which each computer shall return to a specific point in a program, each computer including an arrangement for synchronizing said counter by setting certain of said n digits of the counter to a predetermined binary value by means of a set pulse, and means for producing a synchronizing signal when said counter reaches a predetermined position, and each computer being connected to a common bus line to enable the synchronizing signal produced in one of said computers to be transferred to all of the computers, said arrangement comprising: a blocking logic circuit including a bistable circuit, having a set input, reset input and an output, said bistable circuit being triggered to a set state upon receipt of a signal at said set input and being triggered to a reset state upon receipt of a signal at said reset input; means for transmitting said synchronizing signal to said set input; a pulse generating circuit having an input connected to said bistable circuit and an output for delivering said set pulse to said counter when said bistable circuit is set by said synchronizing signal; and locking means for connecting the output of said pulse generating circuit to said reset input of said bistable circuit in order for said bistable circuit to be reset by said set pulse, whereby said bistable circuit is locked in the reset state as long as said set pulse prevails.
Claim 3
Dependent Claim
70 words
A system as claimed in claim 1, wherein said blocking circuit further includes a delay circuit means which has one input connected to said clock circuit, and another input connected to said output of said bistable circuit, said delay circuit means having an output for supplying said set pulse to said counter in order to set said certain of said n digits of said counter to said predetermined binary value.
Claim 4
Dependent Claim
203 words
A system as claimed in claim 2, wherein said delay circuIt means comprises a first AND-circuit with two inputs and an output, one of said inputs being connected to said clock circuit and the other of said inputs being connected to said output of said bistable circuit, said output of said AND-circuit thus transmitting output signals in response to said stepping pulses when said bistable circuit is in the set state, a first monostable circuit which is set by said output signals from said AND-circuit and automatically resets after a first time interval, during which an output signal is present, a second monostable circuit which is set by said stepping pulses and automatically resets after a second time interval, during which an output signal is present, a second AND-gate with two inputs and an output, one of said inputs being an inverting input and the other of said inputs being a non-inverting input, said inverting input receiving said output signal of said second monostable circuit and said non-inverting input receiving said output signal of said first monostable circuit, whereby said second AND-gate transmits an output signal while said first monostable circuit is set under the condition that said second monostable circuit is reset.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |