US4757442A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor
Assignee: NEC Corp
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Filing: 1986-06-16
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Granted: 1988-07-12
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Expires: 2006-06-16
Abstract
Abstract A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors. The copy request signal causes the master processor to copy the content of the main memory of the normal system to the main memory of each failed system. When the synchronization between the respective systems is established, the device control circuit outputs a restart request signal to the respective processors, thus initiating the execution from a fixed, stored address in a control memory of each processor to enable synchronous starting of all of the processor. The multi-processing device further includes a communication control circuit connected to the common memory bus, thus permitting parallel loading of an initial program to the main memories of the respective systems for achieving recovery in the case where all the systems are asynchronous with each other.
Inventors
- 👤 Hironobu Sakata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1658; G06F11/14; G06F11/1402; G06F11/1415; G06F11/142; G06F11/1423; G06F11/1675; G06F11/1679
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
439 words
A synchronization control system for a multiple computer system comprising: (a) three or more processing system operating in synchronism for executing the same processing, each processing system comprising a processor and a corresponding main memory connected to each other by means of an individual memory bus; (b) a common memory bus connected to all the processors and all the memories of said processing system; (c) an asynchronism detection circuit connected with said processors of said processing systems by means of individual buses, respectively, for monitoring whether outputs of said processing systems are synchronized with each other or not, and producing an asynchronism detection signal indicating an asynchronous state of a processing system which is operating asynchronously with respect to the remaining processing systems; and (d) a device control circuit responsive to sa dasynchronism detection signal supplied from said asynchronism detection circuit for recovering said asynchronous processing systems, said device control circuit including: (1) means for generating a common memory bus select signal to the main memory and the processor of said asynchronous processing system for connecting said main memory and said processor of said asynchronous processing system to said common memory bus, (2) means for generating a master designation signal to the processor of one of said remaining processing systems to designate said processor as a master processor, (3) means fopr generating a copy request signal to all processors of all processing systems, said copy request signal causing the master processor to store processor information of said master processor in the main memory of said master processor and in the main memory of said asynchronous processing system via said common memory bus, and processor information of each of the remaining processors into the corresponding main memory of the remaining processing systems, (4) means, operative upon reception of a copy end signal sent from the processor of said asynchronous processing system for generating (i) a signal for releasing the copy request to allprocessors of said processing systems, (ii) a signal for relasing the master designation of said master processor, and (iii) a signal for releasing the common memory bus selection, (5) means for generating a restart request signal to all processors of said processing systems, said restart request signal causing the processors to recover said processor information stored in said main memories into the processors of said processing systems respectively, and to restart processings of said processors in synchronism with one another, and (6) means for determining whether outputs of said processors of said processing systems are coincident with each other, and in the event of coincidence, to output a signal to all processors for releasing said restart request signal.
Claim 2
Dependent Claim
439 words
A synchronization control system for a multiple computer system comprising: (a) three or more processing system operating in synchronism for executing the same processing, each processing system comprising a processor and a corresponding main memory connected to each other by means of an individual memory bus; (b) a common memory bus connected to all the processors and all the memories of said processing system; (c) an asynchronism detection circuit connected with said processors of said processing systems by means of individual buses, respectively, for monitoring whether outputs of said processing systems are synchronized with each other or not, and producing an asynchronism detection signal indicating an asynchronous state of a processing system which is operating asynchronously with respect to the remaining processing systems; and (d) a device control circuit responsive to sa dasynchronism detection signal supplied from said asynchronism detection circuit for recovering said asynchronous processing systems, said device control circuit including: (1) means for generating a common memory bus select signal to the main memory and the processor of said asynchronous processing system for connecting said main memory and said processor of said asynchronous processing system to said common memory bus, (2) means for generating a master designation signal to the processor of one of said remaining processing systems to designate said processor as a master processor, (3) means fopr generating a copy request signal to all processors of all processing systems, said copy request signal causing the master processor to store processor information of said master processor in the main memory of said master processor and in the main memory of said asynchronous processing system via said common memory bus, and processor information of each of the remaining processors into the corresponding main memory of the remaining processing systems, (4) means, operative upon reception of a copy end signal sent from the processor of said asynchronous processing system for generating (i) a signal for releasing the copy request to allprocessors of said processing systems, (ii) a signal for relasing the master designation of said master processor, and (iii) a signal for releasing the common memory bus selection, (5) means for generating a restart request signal to all processors of said processing systems, said restart request signal causing the processors to recover said processor information stored in said main memories into the processors of said processing systems respectively, and to restart processings of said processors in synchronism with one another, and (6) means for determining whether outputs of said processors of said processing systems are coincident with each other, and in the event of coincidence, to output a signal to all processors for releasing said restart request signal.
Claim 3
Dependent Claim
105 words
A multi-processing device as set forth in claim 1, wherein each of said main memories of said processing systems has a buffer circuit incuding an output buffer connected to the corresponding individual memory bus for outputting a read data to the corresponding processor therethrough, and a pair of tristate input buffers, one connected to said corresponding individual memory bus, the other connected to said common memory bus, wherein said pair of buffers depends upon which control input is enabled by said common memory bus select signal to input a data to be written via either said corresponding individual memory bus or said common memory bus.
Claim 4
Dependent Claim
107 words
A multi-processing device as set forth in claim 1, wherein each of said processors of said respective processing systems has a buffer circuit including an input buffer connected to the corresponding individual memory bus for inputting a read data from the corresponding main memory therethrough, an output buffer connected to said corresponding individual memory bus for outputting a data to be written to said corresponding main memory therethrough, and a tristate output buffer connected to said common memory bus for outputting said data to be written via said common memory bus when a control terminal of said tristate output buffer is enabled by said master designation signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |