Method and apparatus for synchronizing encrypting and decrypting systems

Claim 2

In an encrypted data processing system having encryption and decryption units, said encryption unit containing encryption circuitry for receiving a plurality of plain text data units and for generating encrypted data units, means for computing a first error-detecting code from encrypted data units, and processing apparatus for processing said encrypted data units with said first error-detecting code appended thereto to said decryption unit, said decryption unit having additional processing apparatus, means for computing a second error-detecting code from processed data units, means for comparing said second error-detecting code with said first error-detecting code to determine an error in transmission, and decryption circuitry for generating plain text data units from said processed data units, the improvement comprising: means for initially synchronizing said encryption circuitry and said decryption circuitry, a first sequence counter responsive to input plain text data for generating a first sequence number with a mathematical relationship to the number of data units encrypted by said encryption apparatus since said initial synchronization, means for modifying said first error-detecting code to form a first composite error-detecting code which is uniquely related to said first sequence number and said encrypted data units, a second sequence counter responsive to data units received by said decryption unit for generating a sequence number with said mathematical relationship to the number of data units received by said decryption apparatus since said initial synchronization, means for modifying said second error-detecting code to form a second composite error-detecting code which is uniquely related to said second sequence number and said encrypted data units, and means responsive to said first and second composite error-detecting codes for detecting a mismatch between said codes indicating a loss of synchronization between said encryption and decryption circuitry.

Claim 3

The improvement according to claim 1 wherein said first sequence counter generates a count which is equal to the number of data units encrypted by said encryption apparatus.

Claim 4

The improvement according to claim 1 wherein said second sequence counter generates a count which is directly related to the number of data units validly received by said decryption apparatus.

Claim 5

The improvement according to claim 1 wherein said second sequence counter generates a count which is equal to the number of data units received by said decryption apparatus.

Claim 6

The improvement according to claim 1 wherein means for modifying said first error-detecting code to form a first composite error-detecting code comprises means for causing said first sequence number to be appended to said data units so that said first composite error-detecting code will be computed over said encrypted data units and said first sequence number.

Claim 7

The improvement according to claim 1 wherein means for modifying said second error-detecting code to form a second composite error-detecting code comprises means for causing said second sequence number to be appended to said received data units so that said second composite error-detecting code will be computed over said encrypted data units and said second sequence number.

Claim 8

The improvement according to claim 1 further comprising means responsive to a mismatch between said first and second error-detecting codes for generating a re-processing request to cause said encryption unit to re-process said encrypted data units.

Claim 9

The improvement according to claim 7 further comprising means responsive to said re-processing request for preventing said first sequence counter from counting said re-processed data units.

Claim 10

The improvement according to claim 7 further comprising means responsive to a predetermined number of re-processing requests for causing a resynchronization of said encryption circuitry with said decryption circuitry.

Claim 11

The improvement according to claim 7 further comprising means responsive to a mismatch between said first and second error-detecting codes for resetting said second counter to its count prior to receiving said reprocessed encrypted data units.

Claim 12

The improvement according to claim 1 wherein said first sequence counter is a modulus counter with a predetermined fixed, modulus.

Claim 13

The improvement according to claim 1 wherein said first sequence counter is a modulus counter having a variable modulus.

Claim 14

The improvement according to claim 1 wherein said first sequence counter is a pseudo-random counter generator.

Claim 15

The improvement according to claim 1 wherein data sent to said data processing unit comprises encrypted data units, synchronization flags and error detection codes and said first sequence count includes only said encrypted data units.

Claim 16

The improvement according to claim 1 wherein data sent to said decryption unit comprises encrypted data units, synchronization flags and error detection codes and said first sequence count includes said encrypted data units and a portion of said synchronization flags and error detection codes.

Claim 17

In an encrypted data processing system having encryption and decryption units, said encryption unit containing encryption circuitry for receiving a plurality of plain text data units and for generating encrypted data units, means for computing a first error-detecting code from encrypted data units, and data processing apparatus for processing said encrypted data units with said first error-detecting code appended thereto, said decryption unit having receiver apparatus for receiving encrypted data units, means for computing a second error-detecting code from received data units, means for comparing said second error-detecting code with said first error-detecting code to determine an error in processing, and decryption circuitry for generating plain text data units from said received data units, the improvement comprising: means for initially synchronizing said encryption circuitry and said decryption circuitry, a first sequence counter responsive to input plain text data for generating a first sequence number indicative of the number of data units encrypted by said encryption apparatus since said initial synchronization, means for appending said first sequence number to said encrypted data units prior to said computation of said first error-detecting code so that said first error-detecting code will be computed over said encrypted data units and said first sequence number, a second sequence counter responsive to data units received by said decryption unit for generating a sequence number indicative of the number of data units validly received by said decryption unit since said initial synchronization, means for associating said second sequence number to said received data units so that said second error-detecting code will be computed over said received data units and said second sequence number, and means responsive to said first and second error-detecting codes for detecting a mismatch between said codes indicating a loss of synchronization between said encryption and decryption circuitry.

Claim 18

In an encrypted data processing system having encryption and decryption units, said encryption unit containing encryption circuitry for receiving a plurality of plain text data units and for generating encrypted data units, means for computing a first error-detecting code from encrypted data units, and data processing apparatus for processing said encrypted data units with said first error-detecting code appended thereto, said decryption unit having receiver apparatus for receiving encrypted data units, means for computing a second error-detecting code from received data units, means for comparing said second error-detecting code with said first error-detecting code to determine an error in processing, and decryption circuitry for generating plain text data units from said received data units, the improvement comprising: means for initially synchronizing said encryption circuitry and said decryption circuitry, a first sequence counter responsive to input plain text data for generating a first sequence number indicative of the number of data units encrypted by said encryption apparatus since said initial synchronization, means for appending said first sequence number to said encrypted data units prior to said computation of said first error-detecting code so that said first error-detecting code will be computed over said encrypted data units and said first sequence number, a second sequence counter responsive to data units received by said decryption unit for generating a sequence number indicative of the number of data units validly received by said decryption unit since said initial synchronization, means for associating said second sequence number to said received data units so that said second error-detecting code will be computed over said received data units and said second sequence number, and means responsive to said first and second error-detecting codes for detecting a mismatch between said codes indicating a loss of synchronization between said encryption and decryption circuitry.

Claim 19

The improvement according to claim 16 further comprising means responsive to a mismatch between said first and second error-detecting codes for generating a re-processing request to cause said encryption unit to re-process said encrypted data units.

Claim 20

The improvement according to claim 17 further comprising means responsive to said re-processing request for preventing said first sequence counter from counting said re-processed data units.

Claim 21

The improvement according to claim 17 further comprising means responsive to a predetermined number of re-processing requests for causing a resynchronization of said encryption circuitry with said decryption circuitry.

Claim 22

The improvement according to claim 17 further comprising means responsive to a mismatch between said first and second error-detecting codes for resetting said second counter to its count prior to receiving said reprocessed encrypted data units.

Claim 23

The improvement according to claim 16 wherein said first sequence counter is a modulus counter with a predetermined fixed, modulus.

Claim 24

The improvement according to claim 16 wherein said first sequence counter is a modulus counter having a variable modulus.

Claim 25

The improvement according to claim 16 wherein said first sequence counter is a pseudo-random counter generator.

Claim 26

The improvement according to claim 16 wherein data sent to said data processing unit comprises encrypted data units, synchronization flags and error detection codes and said first sequence count includes only said encrypted data units.

Claim 27

The improvement according to claim 16 wherein data sent to said decryption unit comprises encrypted data units, synchronization flags and error detection codes and said first sequence count includes said encrypted data units and a portion of said synchronization flags and error detection codes.

Claim 28

Apparatus for maintaining the synchronization of encryption and decryption units said encryption unit containing encryption circuitry for receiving a plurality of plain text data units and for generating encrypted data units, said decryption unit having decryption means for generating plain text data units from said encrypted data units, said synchronization apparatus comprising: means for initially synchronizing said encryption circuitry and said decryption circuitry, means responsive to said plain text data for dividing said plain text data into a plurality of blocks and passing each block through said encryption circuitry, means for computing a first error-detecting code from encrypted data units for each block, a first sequence counter responsive to input plain text data for counting the number of data units encrypted by said encryption apparatus since said initial synchronization, means for appending said first sequence number to said encrypted data units for each block prior to said computation of said first error-detecting code so that said first error-detecting code will be computed over said encrypted data units for a data block and said first sequence number, means responsive to encrypted data units and to said error-correcting code for sending said encrypted data units with said error-correcting code appended thereto to said decryption unit receiver means located in said decryption unit for receiving said encrypted data units and said error-detecting code, means responsive to received data units and to said received error-correcting code for storing said received data units and said received error-correcting code a second sequence counter responsive to data units received by said decryption unit for generating a sequence number equal to the number of data units received by said decryption unit since said initial synchronization, means for appending said second sequence number to said received data units means for computing a said second error-detecting code over said received data units and said second sequence number, and means responsive to said stored first error-detecting code and said second error-detecting code for detecting a mismatch between said codes indicating a loss of synchronization between said encryption and decryption circuitry.

Claim 29

Apparatus for maintaining the synchronization of encryption and decryption units said encryption unit containing encryption circuitry for receiving a plurality of plain text data units and for generating encrypted data units, said decryption unit having decryption means for generating plain text data units from said encrypted data units, said synchronization apparatus comprising: means for initially synchronizing said encryption circuitry and said decryption circuitry, means responsive to said plain text data for dividing said plain text data into a plurality of blocks and passing each block through said encryption circuitry, means for computing a first error-detecting code from encrypted data units for each block, a first sequence counter responsive to input plain text data for counting the number of data units encrypted by said encryption apparatus since said initial synchronization, means for appending said first sequence number to said encrypted data units for each block prior to said computation of said first error-detecting code so that said first error-detecting code will be computed over said encrypted data units for a data block and said first sequence number, means responsive to encrypted data units and to said error-correcting code for sending said encrypted data units with said error-correcting code appended thereto to said decryption unit receiver means located in said decryption unit for receiving said encrypted data units and said error-detecting code, means responsive to received data units and to said received error-correcting code for storing said received data units and said received error-correcting code a second sequence counter responsive to data units received by said decryption unit for generating a sequence number equal to the number of data units received by said decryption unit since said initial synchronization, means for appending said second sequence number to said received data units means for computing a said second error-detecting code over said received data units and said second sequence number, and means responsive to said stored first error-detecting code and said second error-detecting code for detecting a mismatch between said codes indicating a loss of synchronization between said encryption and decryption circuitry.

Claim 30

Apparatus according to claim 26 further comprising means responsive to a mismatch between said stored first and said second error-detecting codes for generating a re-transmission request to cause said encryption unit to re-transmit said encrypted data units.

Claim 31

Apparatus according to claim 27 further comprising means responsive to said re-transmission request for preventing said first sequence counter from counting said re-transmitted data units.

Claim 32

Apparatus according to claim 27 further comprising means responsive to a predetermined number of re-transmission requests for causing a resynchronization of said encryption circuitry with said decryption circuitry.

Claim 33

Apparatus according to claim 27 further comprising means responsive to a mismatch between said first and second error-detecting codes for resetting said second counter to its count prior to receiving said retransmitted encrypted data units.

Claim 36

The method according to claim 31 further comprising the further step of: H. generating a re-transmission request to cause said encryption unit to re-transmit said encrypted data units if there is a mismatch between said first and second error-detecting codes.

Claim 37

The method according to claim 31 further comprising the further step of: I. preventing said first sequence counter from counting said re-transmitted data units during the retransmission of said data units.

Claim 38

The method according to claim 33 further comprising the further step of: J. causing a resynchronization of said encryption circuitry with said decryption circuitry after a predetermined number of re-transmission requests.

Claim 39

The method according to claim 34 further comprising the further step of: K. resetting said second counter to its count prior to receiving said retransmitted encrypted data units if there is a mismatch between said first and second error-detecting codes.