Timing monitor circuit for central data processor of digital communication system

Claim 2

In a data processing system having first and second central data processors each including processing circuits and maintenance circuits, said system being adapted wherein only one of said processors is active at one time and the other is standby, timing generating and monitoring circuitry for fault isolation comprising: timing generator circuit meaNs in each of said central processors for generating a plurality of sequentially occurring mutually exclusive timing level signals, a predetermined number of said timing level signals comprising a machine cycle, the timing generator circuit means in the active central processor transmitting said timing level signals to the other central processor; timing monitor circuit means for each central processor and including timing level check circuit means receiving said timing level signals on multiple mutually exclusive circuit means from its associated timing generator circuit means for generating a timing level error level signal either when said timing level signals occur out of a predetermined order or when one of said timing level signals does not occur in a machine cycle; and recovery control circuit means in each of said central processors responsive to said timing level error level signal for initiating a system recovery program.

Claim 3

The system of claim 1 wherein said timing monitor circuit means further comprises repetition rate check circuit means receiving one of said timing level signals during each machine cycle for generating a repetition rate error level signal when the time between sequential ones of said received timing level signals is a predetermined time greater than a normal machine cycle time.

Claim 4

The system of claim 1 wherein said timing level check circuit means further comprises: input combinational logic circuit means receiving said timing level signals for generating sequential signals representative of the expected time of occurrence of said timing level signals; counter circuit means receiving the output signals of said input combinational logic circuit means for generating sequential signals representative of a normally occurring sequence for said timing level signals; and output circuit means responsive to said counter circuit means for generating said timing level error signal when said normally occurring sequence does not occur.

Claim 5

The system of claim 3 wherein said counter circuit means comprises a plurality of individual counter circuits, each counter circuit counting a predetermined sequence of two pulses received from its associated input combinational logic circuit means, whereby the normal sequence of occurrence of said sensed timing level signals circulates a bit through each of said individual counter circuits.

Claim 6

The system of claim 3 wherein said timing level check circuit means further comprises second combinational logic circuit means receiving the output signals of said first-named input combinational logic means thereof for generating signals representative of a normally occurring sequence of predetermined combinations of said input timing level signals; and gating means responsive to predetermined ones of said timing level signals for gating the output signals of said second combinational logic circuit means as a function of time, thereby to generate error signals representative of the absence of a normally occurring sequential timing level signal.

Claim 7

The system of claim 3 wherein said output circuit means of said timing level check circuit comprises third combinational logic circuit means receiving the output signals of said counter circuit means for sampling the same during predetermined times; and timing level error indicator bistable circuit means for storing an error indication of said third combinational logic circuit means, said signal being said timing level error level signal.

Claim 8

The system of claim 3 wherein said input combinational logic circuit means comprises a plurality of logic gates including a first set of said gates and a second set of said gates, said first set of said gates receiving respectively a plurality of even timing level signals and said second set receiving respectively a plurality of odd timing level signals, each of said counter circuits being associated with a plurality of said logic gates.

Claim 9

The system of claim 2 wherein said repetitioN rate circuit means comprises: input gating means including a bistable circuit, said gating means receiving said predetermined timing level pulse in each machine cycle and gating it to one of two outputs depending on the state of said bistable circuit; first and second timing channels, each channel having an input adapted to receive one output of said input gating means, and each channel including monostable circuit means, said repetition rate circuit means having a normal output state representative of an alarm condition wherein said sequential timing pulses are occurring at a first time greater than said predetermined time plus a normal machine cycle time, and a second output state representative of a normal condition wherein said sequential timing pulses are occurring within said first time, and output circuit means receiving the outputs of said timing channels for maintaining the output signal of said repetition rate check circuit in said second state as long as the sequential input pulses are receiving at times less than the pulse widths of the respective monostable circuits.

Claim 10

The system of claim 5 wherein said second combinational logic circuit means further includes an output gate enabled by a signal representative of the associated central processors being active or being diagnosed, whereby the timing level signals for the active central processor are periodically monitored, and the timing level signals for the standby central processor are monitored only under programmed diagnostic routines.

Claim 11

The system of claim 8 further comprising means for coupling the output signal of each timing channel to said input gating means to change the state of said bistable circuit therein, whereby the next sequential input timing pulse is switched to the other timing channel.

Claim 12

The system of claim 10 wherein each of said monostable circuits is responsive only to a pulse edge, and wherein each of said timing channels comprises a second monostable circuit triggered when the first monostable circuit therein is triggered, and after a predetermined delay, actuating said feedback means to switch said bistable circuit in said input gating means.

Claim 13

The system of claim 11 further comprising feedback circuit means in each timing channel responsive to the output signal of said first monostable circuit therein to latch up its associated timing channel and inhibit the reception of subsequent input timing level pulses until its associated first monostable circuit times out.

Claim 14

In a data processing system having first and second central data processors each including processing circuits and maintenance circuits, said system being adapted wherein only one of said processors is active at one time and the other is standby, timing generating and monitoring circuitry for fault isolation comprising: timing generator circuit means in each of said central processors for generating a plurality of sequentially occurring mutually exclusive timing level signals, a predetermined number of said timing level signals comprising a machine cycle, the timing generator means in the active central processor transmitting said timing level signals to the other central processor; timing monitor circuit means for each central processor including timing level check circuit means receiving said timing level signals on multiple mutually exclusive circuit means from its associated timing generator circuit means for generating a timing level error level signal either when said timing level signals occur out of the predetermined order or when one of said timing level signals does not occur in a machine cycle; repetition rate check circuit means receiving a predetermined one of said timing level signals during each machine cycle for generating a repetition rate error level signal when the time between sequential ones of said received timing level signals is a predetermined time greater than a normal machine cycle time; and recovery control circuit means in each of said central processors responsive to said timing level error level signal and to said repetition rate error level signal for initiating a stored system recovery program.

Claim 15

In a data processing system having first and second central data processors each including processing circuits and maintenance circuits, said system being adapted wherein only one of said processors is active at one time and the other is standby, timing generating and monitoring circuitry for fault isolation comprising: timing generator circuit means in each of said central processors for generating a plurality of sequentially occurring mutually exclusive timing level signals, a predetermined number of said timing level signals comprising a machine cycle, the timing generator means in the active central processor transmitting said timing level signals to the other central processor; timing monitor circuit means for each central processor including timing level check circuit means receiving said timing level signals on multiple mutually exclusive circuit means from its associated timing generator circuit means for generating a timing level error level signal either when said timing level signals occur out of the predetermined order or when one of said timing level signals does not occur in a machine cycle; repetition rate check circuit means receiving a predetermined one of said timing level signals during each machine cycle for generating a repetition rate error level signal when the time between sequential ones of said received timing level signals is a predetermined time greater than a normal machine cycle time; and recovery control circuit means in each of said central processors responsive to said timing level error level signal and to said repetition rate error level signal for initiating a stored system recovery program.

Claim 16

The system of claim 13 wherein said timing level check circuit means further comprises: input combinational logic circuit means receiving said timing level signals for generating sequential signals representative of the expected time of occurrence of said timing level signals; counter circuit means receiving the output signals of said input combinational logic circuit means for generating sequential signals representative of a nromally occurring sequence for said timing level signals; and output circuit means responsive to said counter circuit means for generating said timing level error signal when said normally occurring sequence does not occur.

Claim 17

The system of claim 13 wherein said repetition rate check circuit further comprises: input gating means including a bistable circuit, said gating means receiving said predetermined timing level pulse in each machine cycle and gating it to one of two outputs depending on the state of said bistable circuit; first and second timing channels, each channel having an input adapted to receive one output of said input gating means, and each channel including monostable circuit means, said repetition rate circuit means having a normal output state representative of an alarm condition wherein said sequential timing pulses are occurring at a first time greater than said predetermined time plus a normal machine cycle time, and a second output state representative of a normal condition wherein said sequential timing pulses are occurring within said first time, and output circuit means receiving the outputs of said timing channels for maintaining the output signal of said repetition rate check circuit in said second state as long as the sequential input pulses are receiving at times less than the pulse widths of the respective monostable circuits. first and second timing channels, each channel having an input adapted to receive one output of said input gating means, and each channel including monostable circuit means,