Electrical frequency detecting device and method

Claim 2

An electrical device for determining whether a plurality of input pulses occur at a repetition rate above or below a given reference rate and for producing an output signal representative of the determination made thereby, said device comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging said capacitor, a detecting circuit connected with said capacitor for producing an output signal when the voltage across said capacitor reaches a predetermined value, the values of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period equal to the period between pulses occurring at said reference rate of repetition, an input terminal, a gated discharge circuit connected across said capacitor and responsive to input pulses applied to said input terminal for discharging said capacitor to said discharged condition during the appearance of each of said input pulses and for permitting said capacitor to charge during the period between successive ones of said input pulses, and means connected with said input terminal for converting an input signal of cyclical waveform into input pulses such as aforesaid which input pulses are applied to said input terminal and occur at a rate equal to the frequency of said input signal.

Claim 3

An electrical device as defined in claiM 1 further characterized by said gated discharge circuit including a transistor having a base terminal and two main terminals, means connecting one of said main terminals to one side of said capacitor, a diode, means connecting the other of said main terminals of said transistor to the other side of said capacitor through said diode, and means for applying said input pulses to said base terminal of said transistor.

Claim 4

An electrical device for determining whether a plurality of input pulses occur at a repetition rate above or below a given reference rate and for producing an output signal representative of the determination made thereby, said device comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging said capacitor, a detecting circuit connected with said capacitor including means for producing an output pulse when the voltage across said capacitor reaches a predetermined value, the value of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period equal to the period between pulses occurring at said reference rate of repetition, an input terminal, and a gated discharge circuit connected across said capacitor and responsive to input pulses applied to said input terminal for discharging said capacitor to said discharged condition during the appearance of each of said input pulses and for permitting said capacitor to charge during the period between successive ones of said input pulses.

Claim 5

An electrical device for determining whether a plurality of input pulses occur at a repetition rate above or below a given reference rate and for producing an output signal representative of the determination made thereby, said device comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging said capacitor, a detecting circuit connected with said capacitor including means for producing an output pulse when the voltage across said capacitor reaches a predetermined value, the value of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period equal to the period between pulses occurring at said reference rate of repetition, an input terminal, and a gated discharge circuit connected across said capacitor and responsive to input pulses applied to said input terminal for discharging said capacitor to said discharged condition during the appearance of each of said input pulses and for permitting said capacitor to charge during the period between successive ones of said input pulses.

Claim 6

An electrical device as defined in claim 3 further characterized by said detecting circuit including a unijunction transistor connected with said capacitor so as to be triggered to a conducting state and provide a discharge circuit for said capacitor when the voltage across said capacitor reaches said predetermined voltage.

Claim 7

An electrical device as defined in claim 4 further characterized by said unijunction transistor having its emitter terminal connected to one side of said capacitor and having one of its base terminals connected to the other side of said capacitor through a resistor.

Claim 8

An electrical device as defined in claim 4 further characterized by said unijunction transistor having its emitter terminal connected to the junction of said capacitor and said charging circuit resistance, said unijunction transistor further having one of its base terminals connected to one side of said voltage source through a first resistance and having the other of its base terminals connected to the other side of said voltage source through a second resistance.

Claim 9

An electrical device as defined in claim 3 further characterized by said detecting circuit including a unijunction transistor having its emitter terminal connected to the junction of said capacitor and said charging circuit resistance, said unijunction transistor having one of its base terminals connected to one side of said voltage source through a first resistance and having the other of its base terminals connected to the other side of said voltage source through a second resistance, said gated discharge circuit including a transistor having emitter, collector and base terminals, said transistor having its emitter terminal connected to said one side of said capacitor and having its collector terminal connected to the other side of said capacitor through a diode, a resistor connected between said collector terminal and said other side of said supply voltage and means for applying said input pulses to the base terminal of said transistor.

Claim 10

An electrical device as defined in claim 3 further characterized by means connected with said detecting circuit for producing an output pulse whenever no output pulse is produced by said detecting circuit during the interval between two successive ones of said input pulses.

Claim 11

An electrical device as defined in claim 8 further characterized by said pulse produCing means comprising a flip-flop connected with said detecting circuit and arranged to be reset to zero condition by an output pulse from said detecting circuit, means for transmitting said input pulses to said flip-flop for setting said flip-flop to its other condition in response to such input pulses, and a NAND gate circuit having as inputs thereto said input pulses and the output of said flip-flop and adapted to produce output pulses occurring simultaneously with said input pulses only when said flip-flop is in its set condition at the time of the occurrence of said input pulses.

Claim 12

An electrical device for determining whether a plurality of input pulses occur at a repetition rate falling within or without a given band of repetition rates and for producing an output signal representative of the determination made thereby, said device comprising an input terminal to which input pulses such as aforesaid are applied, a low limit detector directly connected to said input terminal, said low limit detector being responsive to input pulses supplied thereto from said input terminal and including means for producing output pulses when said input pulses occur at a rate falling on one side of the low limit of said band and for producing no output pulses when said input pulses occur at a rate falling on the other side of said low limit of said band, a high limit detector also directly connected to said input terminal, said high limit detector being responsive to input pulses supplied thereto from said input terminal and including means for producing output pulses when said input pulses occur at a rate falling on one side of the high limit of said band and for producing no pulses when said input pulses occur at a rate falling on the other side of said high limit of said band, and a logic gate having as inputs thereto the outputs of said low and high limit detectors.

Claim 13

An electrical device for determining whether a plurality of input pulses occur at a repetition rate falling within or without a given band of repetition rates and for producing an output signal representative of the determination made thereby, said device comprising an input terminal to which input pulses such as aforesaid are applied, a low limit detector directly connected to said input terminal, said low limit detector being responsive to input pulses supplied thereto from said input terminal and including means for producing output pulses when said input pulses occur at a rate falling on one side of the low limit of said band and for producing no output pulses when said input pulses occur at a rate falling on the other side of said low limit of said band, a high limit detector also directly connected to said input terminal, said high limit detector being responsive to input pulses supplied thereto from said input terminal and including means for producing output pulses when said input pulses occur at a rate falling on one side of the high limit of said band and for producing no pulses when said input pulses occur at a rate falling on the other side of said high limit of said band, and a logic gate having as inputs thereto the outputs of said low and high limit detectors.

Claim 14

An electrical device as defined in claim 10 further characterized by said means of said low limit detector comprising means for producing output pulses when said input pulses occur at a rate below the low limit of said band and for producing no output pulses when said input pulses occur at a rate above the low limit of said band, and said means of said high limit detector comprising means for producing output pulses when said input pulses occur at a rate above the high limit of said band and for producing no pulses when said input pulses occur at a rate below said high limit of said band.

Claim 15

An electrical device as defined in claim 10 further characterized by at least one of said detectors comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging said capacitor, a detecting circuit connected with said capacitor for producing an output signal when the voltage across said capacitor reaches a predetermined value, the values of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period equal to the period between pulses occurring at a rate of repetition equal to an associated one of the limit rates of said band, and a gated discharge circuit connected across said capacitor and responsive to said input pulses for discharging said capacitor to said discharged condition during the appearance of each of said input pulses.

Claim 16

An electrical device as defined in claim 12 further characterized by said detecting circuit including means for producing an output voltage pulse when the voltage across said capacitor reaches said predetermined value.

Claim 17

An electrical device as defined in claim 13 further characterized by said detecting circuit including a unijunction transistor connected with said capacitor so as to be triggered to a conducting state and provide a discharge circuit for said capacitor when the voltage across said capacitor reaches said predetermined voltage.

Claim 18

An electricaL device as defined in claim 10 further characterized by at least one of said detectors comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging in said capacitor, a detecting circuit including a unijunction transistor connected with said capacitor so as to be triggered to a conducting state and provide a discharge circuit for said capacitor when the voltage across said capacitor reaches said predetermined value, means for producing an output voltage pulse in response to the triggering of said unijunction transistor, the values of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period equal to the period between pulses occurring at a rate of repetition equal to an associated one of the limit rates of said band, a gated discharge circuit connected across said capacitor and responsive to said input pulses for discharging said capacitor to said discharged condition during the appearance of each of said input pulses, a flip-flop connected with said detecting circuit and arranged to be reset to zero condition by an output pulse from said detecting circuit, means for transmitting said input pulses to said flip-flop for setting said flip-flop to its other condition in response to the trailing edge of such input pulse, and an NAND gate circuit having as inputs thereto said input pulses and the output of said flip-flop for producing output pulses occurring simultaneously with said input pulses only when said flip-flop is in its set condition at the time of the occurrence of said input pulses, the output of said NAND gate constituting the output which is transmitted to said NOR gate.

Claim 19

A device as defined in claim 10 further characterized by an output flip-flop having set and reset terminals, means directly connecting the reset terminal of said output flip-flop to the output of said NOR gate, and a set unit connected between said output of said NOR gate and said set terminal of said output flip-flop, said set unit including means for producing output pulses transmitted to said set terminal of said output flip-flop when no pulses appear at the output of said NOR gate and for producing no pulses for transmission to said set terminal of said output flip-flop when pulses do occur at the output terminal of said NOR gate.

Claim 20

An electrical device as defined in claim 16 further characterized by said set unit comprising a capacitor, a voltage source, a charging circuit including a resistance connected in series with said capacitor across said voltage source for charging said capacitor, a detecting circuit connected with said capacitor for producing an output signal whenever the voltage across said capacitor reaches a predetermined value, said detecting circuit including a unijunction transistor connected with said capacitor so as to be triggered to a conducting state and provide a discharge circuit for said capacitor when the voltage across said capacitor reaches said predetermined voltage, and means for producing an output pulse in response to the triggering of said unijunction transistor, the values of said capacitor, said voltage source and said resistance being such that said capacitor is charged from a discharged condition to said predetermined voltage during a period longer than the period between pulses occurring at said low limit rate, and a gated discharge circuit connected across said capacitor and responsive to pulses received from said NOR gate for discharging said capacitor to said discharged condition during the receipt of each of said latter pulses from said NOR gate.

Claim 21

An electrical device for determining whether a plurality of input pulses occur at a repetition rate above or below a given reference rate and for producing an output signal representative of the determination made thereby, said device comprising a timing means hAving a predetermined timing interval and being operable to reset itself to an initial condition with regard to said timing interval and to produce an output signal upon the running of said timing interval, said timing means having an input terminal and being adapted to run when no input pulse appears at said input terminal, and means responsive to the appearance of an input pulse at said input terminal for resetting said timing means to said initial condition.

Claim 22

An electrical device for determining whether a plurality of input pulses occur at a repetition rate above or below a given reference rate and for producing an output signal representative of the determination made thereby, said device comprising a timing means hAving a predetermined timing interval and being operable to reset itself to an initial condition with regard to said timing interval and to produce an output signal upon the running of said timing interval, said timing means having an input terminal and being adapted to run when no input pulse appears at said input terminal, and means responsive to the appearance of an input pulse at said input terminal for resetting said timing means to said initial condition.

Claim 23

An electrical device as defined in claim 18 further characterized by a means connected with said input terminal for converting an input signal of cyclical waveform into input pulses such as aforesaid which input pulses are applied to said input terminal and which occur at a rate equal to the frequency of said input signal.

Claim 24

An electrical device as defined in claim 18 further characterized by said timing means having an output terminal and being operable to produce an output voltage pulse at said output terminal upon the running of said timing interval, and means connected with said output terminal of said timing means and having its own output terminal for producing an output pulse at said latter output terminal whenever no output pulse appears at said output terminal of said timing means during the interval between two successive ones of said input pulses.

Claim 25

In an electrical device for determining whether a plurality of input pulses occur at a repetition rate falling within or without a given band of repetition rates, the combination comprising an input terminal, a first timing means having a first predetermined timing interval and operable to produce a first output signal upon the running of said first timing interval, said first timing means being connected with said input terminal and being adapted to run when no input pulse appears at said input terminal, a second timing means having a second predetermined timing interval different from said first timing interval and operable to produce a second output signal upon the running of said second timing interval, said second timing means also being connected with said input terminal and being adapted to run when no input pulse appears at said input terminal, and means for resetting both said first and said second timing means to initial conditions to start new timing cycles in response to the appearance of a pulse at said input terminal.

Claim 26

In an electrical device for determining whether a plurality of input pulses occur at a repetition rate falling within or without a given band of repetition rates, the combination comprising an input terminal, a first timing means having a first predetermined timing interval and operable to produce a first output signal upon the running of said first timing interval, said first timing means being connected with said input terminal and being adapted to run when no input pulse appears at said input terminal, a second timing means having a second predetermined timing interval different from said first timing interval and operable to produce a second output signal upon the running of said second timing interval, said second timing means also being connected with said input terminal and being adapted to run when no input pulse appears at said input terminal, and means for resetting both said first and said second timing means to initial conditions to start new timing cycles in response to the appearance of a pulse at said input terminal.

Claim 27

A combination defined in claim 21 further characterized by means connected with said first timing means for producing a third output signal whenever no first output signal is produced by said first timing means during a interval between two successive ones of said input pulses, a logic gate having two input terminals and means for transmitting said second output signal and said third output signal respectively to said logic gate as inputs thereto.

Claim 28

The combination defined in claim 22 further characterized by said logic gate having an output terminal and being operable to produce a fourth output signal at its said output terminal in response to the appearance at either of its two said input terminals of either said second or said third output signals, a third timing means connected with said output terminal of said logic gate having a third predetermined timing interval and operable to produce a fifth output signal upon the running of said third timing interval, said third timing means being adapted to run when said fifth output signal is absent from said output terminal of said logic gate, and means for resetting said third timing means to an initial condition to start a new timing interval in response to the appearance of said fifth output signal at said output terminal of said logic gate.

Claim 29

The combination defined in claim 23 further characterized by said third timing means having an output terminal at which said fifth output signal appears, a flip-flop having a set terminal and a reset terminal, means connecting said output terminal of said logic gate to the said set terminal of said flip-flop so that saId flip-flop is set by said fourth output signal, and means connecting said output terminal of said third timing means to said flip-flop so that said flip-flop is reset by said fifth output signal.

Claim 30

The combination defined in claim 24 further characterized by said first, second and third timing means, said means connected with said first timing means for producing a third output signal, and said logic gate being so constructed that all of said first, second, third, fourth and fifth output signals are in the form of voltage pulses.