US4785453A
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US
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High level self-checking intelligent I/O controller
Assignee: Tandem Computers Inc
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Filing: 1987-06-30
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Granted: 1988-11-15
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Expires: 2007-06-30
Abstract
Abstract The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates the checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate internal faults. Mis-compares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.
Inventors
- 👤 Strikumar R. Chandran
- 👤 Edward J. Rhodes
- 👤 Albert S. Lui
- 👤 Mark S. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/16; G06F11/1629; G06F11/1641; G06F11/1654; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
244 words
A dual modular redundant processor apparatus for assuring data integrity, said apparatus comprising: first and second processor means for respectively producing true and complement operating signals in the absence of any abnormal condition in the dual modular redundant processor apparatus; internal system bus means coupled to the first and second processor means for comunicating the operating signals; means for producing a periodic clock signal; synchronizer means coupled to the internal system bus means for synchronizing leading edges of true and complement pairs of the operating signals produced by said first and second processor means, the synchronizer means including means responsive to the periodic clock signal for cyclically sampling the true and complement pairs of the operating signals, and output means coupled to the sampling means and responsive to the clock signal for producing synchronized operating signals having synchronized leading edges and corresponding to the true and complement pairs of the operating signals; checker means responsive to the synchronized operating signals for determining whether complementation exists therebetween, said checker means generating a dual-railed error signal in the event of absence of such complementation; and error detector means for receiving the error signals from said checker means, said error detector means generating and transmitting to each of said first and second processor means an error detected signal, whereby said first and second processor means can take appropriate action in response to the true and complement operating signals being detected as not having the predetermined logical relationship.
Claim 2
Dependent Claim
244 words
A dual modular redundant processor apparatus for assuring data integrity, said apparatus comprising: first and second processor means for respectively producing true and complement operating signals in the absence of any abnormal condition in the dual modular redundant processor apparatus; internal system bus means coupled to the first and second processor means for comunicating the operating signals; means for producing a periodic clock signal; synchronizer means coupled to the internal system bus means for synchronizing leading edges of true and complement pairs of the operating signals produced by said first and second processor means, the synchronizer means including means responsive to the periodic clock signal for cyclically sampling the true and complement pairs of the operating signals, and output means coupled to the sampling means and responsive to the clock signal for producing synchronized operating signals having synchronized leading edges and corresponding to the true and complement pairs of the operating signals; checker means responsive to the synchronized operating signals for determining whether complementation exists therebetween, said checker means generating a dual-railed error signal in the event of absence of such complementation; and error detector means for receiving the error signals from said checker means, said error detector means generating and transmitting to each of said first and second processor means an error detected signal, whereby said first and second processor means can take appropriate action in response to the true and complement operating signals being detected as not having the predetermined logical relationship.
Claim 3
Dependent Claim
42 words
The apparatus as claimed in claim 1 wherein the true and complement operating signals respectively include true and complement address signals, said checker means being operable to determine whether the true and complement address signals have a complemented relationship to each other.
Claim 4
Dependent Claim
44 words
The apparatus as claimed in claim 2 wherein the true and complement operating signals respectively further include true and complement data signals, said checker means being operable to determine whether the true and complement data signals have a complement of relationship to each other.
Claim 5
Dependent Claim
24 words
The apparatus as claimed in claim 2 further comprising: parity checker means for checking the parity of each of the true and complement addresses.
Claim 6
Dependent Claim
171 words
A self-checking intelligent input/output controller, comprising: dual redundant processor means configured to respectively issue true and complement operating signals and a true and complement pair of control signals; synchronizer means operable to receive and synchronize the leading edges of the true and complement pair of control signals, the synchronizing means including first circuit means for periodically sampling each one of the true and complement pair of control signals, and second circuit means for comparing the sampled pair of true and complement pair of control signals to produce therefrom true and complement output signals having synchronized leading edges when the leading edges of the true and complement pair of control signals occur within a predetermined time period; checker means having morphic reduction circuits coupled to receive and compare the true operating and output signals with the complement operating and output signals to produce a true and complement error signal indicative of a miscompare; and circuit means, including the dual redundant processors, operable in a predetermined manner in response to the error signals.
Claim 7
Dependent Claim
171 words
A self-checking intelligent input/output controller, comprising: dual redundant processor means configured to respectively issue true and complement operating signals and a true and complement pair of control signals; synchronizer means operable to receive and synchronize the leading edges of the true and complement pair of control signals, the synchronizing means including first circuit means for periodically sampling each one of the true and complement pair of control signals, and second circuit means for comparing the sampled pair of true and complement pair of control signals to produce therefrom true and complement output signals having synchronized leading edges when the leading edges of the true and complement pair of control signals occur within a predetermined time period; checker means having morphic reduction circuits coupled to receive and compare the true operating and output signals with the complement operating and output signals to produce a true and complement error signal indicative of a miscompare; and circuit means, including the dual redundant processors, operable in a predetermined manner in response to the error signals.
Claim 8
Dependent Claim
17 words
The self-checking intelligent input/output controller of claim 5, wherein the operating signals include address and data signals.
Claim 9
Dependent Claim
35 words
The self-checking intelligent input/output controller of claim 6, wherein the circuit means includes means for halting operating of at least one of the dual redundant processors in response to the true and complement error signal.
Claim 10
Dependent Claim
70 words
The self-checking intelligent input/output controller of claim 5, including memory means and bus means coupling the dual redundant processor means to the memory means for communicating certain of the operating signals therebetween, the true and complement operating signals respectively including true and complement address signals operable to cyclicly access the memory means, the checker means being operable each memory cycle to receive and compare the true and complement address signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |