Data processing system having redundant control processors for fault detection

Claim 1

a partially redundant data processing system comprising: a control store for storing a microprogram constituted by a plurality of microinstructions; redundant first and second control processors coupled to said control store for commonly receiving microinstructions from said control store and for simultaneously executing identical data processing under control of said microinstructions, the first and second control processors delivering predetermined microinstructions and memory addresses each time said first and second control processors receive microinstructions from said control store; microinstruction input means for simultaneously supplying to said first and second control processors microinstructions read out from said control store; a cache memory for storing a copy of a part of data stored in a main memory; a first comparator circuit connected to said first and second control processors, for comparing micro-addresses delivered from said first and second control processors to deliver a first non-coincidence signal when the micro-addresses do not coincide with each other; micro-address output means including a first multiplexer for selecting one of said micro-addresses delivered from said first and second control processors and supplying the selected one micro-address to said control store; a second comparator circuit connected between said cache memory and said first and second control processors, for comparing memory addresses delivered from said first and second control processors to deliver a second non-coincidence signal when the memory addresses do not coincide with each other; CPU-to-cache interface means including a second multiplexer for selecting one of said memory addresses delivered from said first and second control processors and supplying the selected one memory address to said cache memory; data input means for simultaneously supplying data read out from said cache memory to said first and second control processors; and a fault processing circuit connected to receive the first and second non-coincidence signals of said first and second comparator circuits and connected to said first and second control processors for supplying a clock stop signal to said first and second control processors when a non-coincidence signal is delivered from at least one of said first and second comparator circuits so as to stop temporarily execution of said microinstructions at said first and second control processors.