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US5146589A
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Refresh control for dynamic memory in multiple processor system
Assignee: Tandem Computers Inc
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Filing: 1990-12-17
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Granted: 1992-09-08
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Expires: 2010-12-17
Abstract
Abstract A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed. The refresh cycles are interposed at the same point in the instruction stream for each of the three CPUs by counting instruction execution cycles separately in each CPU, and interrupting to do a refresh cycle when a given count is reached. Stall cycles are also counted, and when long periods of stalls occur then more than one refresh cycle is interposed to catch up to the needed refresh schedule.
Inventors
- 👤 Charles E. Peet, Jr.
- 👤 John D. Allison
- 👤 Kenneth C. Debacker
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/16; G06F11/1629; G06F11/1641; G06F11/1658; G06F11/1666; G06F11/1675; G06F11/1683; G06F11/1687; G06F11/1691; G06F11/18; G06F11/183; G06F11/184; G06F11/185; G06F11/20; G06F11/2017; G06F9/3824; G06F9/3836; G06F9/3851; G06F9/3885; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/08; G06F11/10; G06F11/1008; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1415; G06F11/1679; G06F11/181; G06F11/182; G06F11/2015; G06F2201/00; G06F2201/85; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
182 words
A computer system, comprising: a) a plurality of CPUs each executing the same instruction stream, each CPU having a clock to define machine cycles, the CPUs being clocked independently of one another by said clocks, said machine cycles providing execution cycles when instructions of said instruction stream execute or providing stall cycles when an instructions of said instruction stream do not execute; b) each of the CPUs having a first counter to count execution cycles but not stall cycles, and having a second counter to count stall cycles; c) each of said CPUs having a local memory requiring periodic refresh; d) each of said CPUs having a separate refresh control responsive to a given count in said first counter of the CPU to initiate a refresh of said local memory of the CPU, and responsive to said second counter to perform a number of cycles of refresh of said local memory depending upon a selected count of the second counter, said refresh of said local memory occurring at the execution of an instruction in said instruction steam in all of said CPUs.
Claim 2
Dependent Claim
182 words
A computer system, comprising: a) a plurality of CPUs each executing the same instruction stream, each CPU having a clock to define machine cycles, the CPUs being clocked independently of one another by said clocks, said machine cycles providing execution cycles when instructions of said instruction stream execute or providing stall cycles when an instructions of said instruction stream do not execute; b) each of the CPUs having a first counter to count execution cycles but not stall cycles, and having a second counter to count stall cycles; c) each of said CPUs having a local memory requiring periodic refresh; d) each of said CPUs having a separate refresh control responsive to a given count in said first counter of the CPU to initiate a refresh of said local memory of the CPU, and responsive to said second counter to perform a number of cycles of refresh of said local memory depending upon a selected count of the second counter, said refresh of said local memory occurring at the execution of an instruction in said instruction steam in all of said CPUs.
Claim 3
Dependent Claim
24 words
A system according to claim 1 wherein said CPUs are loosely synchronized by voting access to a common memory accessable by all said CPUs.
Claim 4
Dependent Claim
22 words
A system according to claim 1 wherein there are three said CPUs and wherein said CPUs access a duplicated common global memory.
Claim 5
Independent Claim
165 words
A method of operating a computer system, comprising the steps of: a) executing instructions of the same instruction stream in each one of a plurality of CPUs, the CPUs each having a separate clock and being clocked independently of one another by said separate clocks to provide machine cycles including execution cycles and stall cycles, the CPUs executing said execution cycles when said instructions are ready for execution or executing said stall cycles when said instructions are not ready for execution; b) counting execution cycles but not stall cycles in each of the CPUs in a first counter, and counting stall cycles in each CPU in a second counter; c) each of said CPUs accessing a separate local memory requiring periodic refresh; d) and initiating refresh of said local memory separately for each CPU responsive to a given count in said first counter of each CPU and performing a number of cycles of refresh depending upon the count in said second counter of the CPU.
Claim 6
Independent Claim
165 words
A method of operating a computer system, comprising the steps of: a) executing instructions of the same instruction stream in each one of a plurality of CPUs, the CPUs each having a separate clock and being clocked independently of one another by said separate clocks to provide machine cycles including execution cycles and stall cycles, the CPUs executing said execution cycles when said instructions are ready for execution or executing said stall cycles when said instructions are not ready for execution; b) counting execution cycles but not stall cycles in each of the CPUs in a first counter, and counting stall cycles in each CPU in a second counter; c) each of said CPUs accessing a separate local memory requiring periodic refresh; d) and initiating refresh of said local memory separately for each CPU responsive to a given count in said first counter of each CPU and performing a number of cycles of refresh depending upon the count in said second counter of the CPU.
Claim 7
Dependent Claim
30 words
A method according to claim 4 wherein said step of initiating said refresh is done at execution of the same instruction in said instruction stream in each of said CPUs.
Claim 8
Dependent Claim
24 words
A method according to claim 4 wherein said CPUs are loosely synchronized by voting access to a common memory accessable by all said CPUs.
Claim 9
Dependent Claim
22 words
A method according to claim 4 wherein there are three said CPUs and wherein said CPUs access a duplicated common global memory.
Claim 10
Independent Claim
110 words
A method of refreshing a memory accessed by a processor, comprising the steps of: a) counting cycles during which said processor executes an instruction to provide a first count; b) counting cycles during which said processor is stalled to provide a second count; c) interrupting executing of instructions by said processor to refresh said memory when said first count reaches a selected value, said refresh of said memory upon said step of interrupting being for a number of refresh cycles determined by said second count, said number of refresh cycles being increased by one for each time the value of said second count exceeds the value of said first count.
Claim 11
Independent Claim
110 words
A method of refreshing a memory accessed by a processor, comprising the steps of: a) counting cycles during which said processor executes an instruction to provide a first count; b) counting cycles during which said processor is stalled to provide a second count; c) interrupting executing of instructions by said processor to refresh said memory when said first count reaches a selected value, said refresh of said memory upon said step of interrupting being for a number of refresh cycles determined by said second count, said number of refresh cycles being increased by one for each time the value of said second count exceeds the value of said first count.
Claim 12
Dependent Claim
33 words
A method according to claim 8 wherein said memory is a local memory and said processor also accesses a common memory, and including the step of accessing said common memory by another processor.
Claim 13
Independent Claim
143 words
A method of operating a computer system having a plurality of processors which are executing the same instruction stream, each of said processors making the same accesses to a separate local memory for the same data items, comprising the steps of: a) separately counting cycles during which each said processor executes an instruction to provide a first count for each processor; b) separately counting cycles during which each said processor is stalled to provide a second count for each processor; c) interrupting executing of instructions by each said processor to refresh said separate local memory for each said processor when said first count reaches a selected value, for a number of refresh cycles determined by said second count, said number of refresh cycles being increased by one for each time the value of said second count exceeds the value of said first count.
Claim 14
Independent Claim
143 words
A method of operating a computer system having a plurality of processors which are executing the same instruction stream, each of said processors making the same accesses to a separate local memory for the same data items, comprising the steps of: a) separately counting cycles during which each said processor executes an instruction to provide a first count for each processor; b) separately counting cycles during which each said processor is stalled to provide a second count for each processor; c) interrupting executing of instructions by each said processor to refresh said separate local memory for each said processor when said first count reaches a selected value, for a number of refresh cycles determined by said second count, said number of refresh cycles being increased by one for each time the value of said second count exceeds the value of said first count.
Claim 15
Dependent Claim
19 words
A method according to claim 10 including the step of accessing a common memory by each of said processors.
Claim 16
Dependent Claim
25 words
A method according to claim 11 wherein said step of accessing said common memory includes voting access requests from said processors to said common memory.
Claim 17
Dependent Claim
20 words
A method according to claim 11 including the step of clocking each of said processors separately by separate clock sources.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-08 | 1996-03-09 | 1996-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-08 | 2000-03-09 | 2000-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-08 | 2004-03-09 | 2004-09-08 | $7700.00 | Window Closed / Lapsed |