US4873685A
Expired / Lapsed
US
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Self-checking voting logic for fault tolerant computing applications
Assignee: Boeing Co
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Filing: 1988-05-04
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Granted: 1989-10-10
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Expires: 2008-05-04
Abstract
Abstract An apparatus and method for providing self-checking voting logic for fault tolerant computing applications. The apparatus comprises a voting circuitry for producing a voting circuit output signal based upon a majority of triplicated logic output signals, unanimous circuitry for producing a unanimous circuit output signal that represents whether or not all of said triplicated logic output signal values are equal or not and self-checking circuitry for monitoring the validity of operation of the voting and the unanimous circuitry as well as said self-checking circuitry itself.
Inventors
- 👤 Hugh L. Millis, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187; G06F11/22; G06F11/2205; G06F11/2215
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
120 words
An apparatus comprising in combination: a voting circuit means for producing a voting circuit output signal based upon a majority value of triplicated logic output signals 01, 02, and 03; a unanimous circuit means for producing a unanimous circuit output signal representing whether or not all of said triplicated logic output signal values are equal or not; and a self-checking means for monitoring operational validity of said voting and said unanimous circuit means, and said self-checking means, said self-checking, voting, and unanimous circuit means operating independently from triplicated logic circuits producing said triplicated logic output signals, and said self-checking circuit means receiving said output signals 01, 02, and 03, said voting circuit output signal, and said unanimous circuit output signal.
Claim 2
Independent Claim
120 words
An apparatus comprising in combination: a voting circuit means for producing a voting circuit output signal based upon a majority value of triplicated logic output signals 01, 02, and 03; a unanimous circuit means for producing a unanimous circuit output signal representing whether or not all of said triplicated logic output signal values are equal or not; and a self-checking means for monitoring operational validity of said voting and said unanimous circuit means, and said self-checking means, said self-checking, voting, and unanimous circuit means operating independently from triplicated logic circuits producing said triplicated logic output signals, and said self-checking circuit means receiving said output signals 01, 02, and 03, said voting circuit output signal, and said unanimous circuit output signal.
Claim 3
Dependent Claim
35 words
The apparatus as set forth in claim 1, wherein said voting circuit means comprises: an electrical circuit that produces said voting circuit output value mechanized by a logical equation wherein said voting circuit output value=0102+0103+0203.
Claim 4
Dependent Claim
40 words
The apparatus as set forth in claim 1, wherein said unanimous circuit means comprises: an electrical circuit that produces said unanimous circuit output value mechanized by the following logical equation wherein said unanimous circuit output value=01 02 03+01' 02' 03'.
Claim 5
Dependent Claim
36 words
The apparatus as set forth in claim 1, wherein said self-checking means comprises, an electrical circuit that produces an operational validity signal value mechanized by the following logical equation wherein said operational validity signal=logic signal T⊕(0102+0103+0203)⊕(010203+01'02'03')⊕(01⊕02⊕03).
Claim 6
Dependent Claim
122 words
The apparatus as set forth in claim 1, wherein said self-checking means comprises: a triple input EXCLUSIVE OR circuit having an output wherein said inputs of said triple input EXCLUSIVE OR circuit are connected to said triplicated logic output signals; a two input, single output EXCLUSIVE OR circuit whose inputs are respectively connected to said triple input EXCLUSIVE OR circuit output and to a logic signal T; and said single output of said two input, single output EXCLUSIVE OR circuit being connected in conjunction with said unanimous circuit output signal, and with said voting circuit output signal to a second triple input EXCLUSIVE OR circuit wherein said second triple input EXCLUSIVE OR circuit produces an output representing results of said self-checking means.
Claim 7
Dependent Claim
43 words
The apparatus as set forth in claim 4 wherein said logical signal T is toggled between a logic "0" state and a logic "1" state to test for correct operability of said self-checking means, said toggling operating independently from monitored triplicated logic circuits.
Claim 8
Independent Claim
215 words
An apparatus comprising, in combination: a series of voting circuit means each respectively receiving a series of triplicated logic output signals 01, 02, 03, wherein each of said voting circuit means produces an output signal V corresponding to a majority of values of said triplicated logic output signals received from associated triplicated logic circuitry; a series of unanimous circuit means for receiving said series of triplicated logic output signals, wherein each of said unanimous circuit means produces an output signal U representing whether or not its received triplicated logic outut signals agree or not; a series of self-checking circuit means for detecting failures in said series of voting circuit means, said series of unanimous circuit means, and in said self-checking circuit means, wherein each respective self-checking circuit means of said series of self-checking circuit means functions independently from associated triplicated logic circuitry to produce an error signal F based upon said detection, and wherein each respective self-checking circuit means receives said output signals 01, 02, and 03 from said associated triplicated logic circuitry, said output signal V from a voting circuit means, and said output signal U from a unanimous circuit means; and a multiple input self-checking circuit means for "OR"ing said F error signals in conjunction with a self-test logic signal T a .
Claim 9
Independent Claim
215 words
An apparatus comprising, in combination: a series of voting circuit means each respectively receiving a series of triplicated logic output signals 01, 02, 03, wherein each of said voting circuit means produces an output signal V corresponding to a majority of values of said triplicated logic output signals received from associated triplicated logic circuitry; a series of unanimous circuit means for receiving said series of triplicated logic output signals, wherein each of said unanimous circuit means produces an output signal U representing whether or not its received triplicated logic outut signals agree or not; a series of self-checking circuit means for detecting failures in said series of voting circuit means, said series of unanimous circuit means, and in said self-checking circuit means, wherein each respective self-checking circuit means of said series of self-checking circuit means functions independently from associated triplicated logic circuitry to produce an error signal F based upon said detection, and wherein each respective self-checking circuit means receives said output signals 01, 02, and 03 from said associated triplicated logic circuitry, said output signal V from a voting circuit means, and said output signal U from a unanimous circuit means; and a multiple input self-checking circuit means for "OR"ing said F error signals in conjunction with a self-test logic signal T a .
Claim 10
Dependent Claim
38 words
The apparatus as set forth in claim 7, wherein said series of voting circuit means comprises: multiple electrical circuits which each individually produce said output signal V mechanized by the following logical equation wherein each said signal V=0102+0103+0203.
Claim 11
Dependent Claim
36 words
The apparatus as set forth in claim 7, wherein said series of unanimous circuit means comprises: electrical circuits which produce said series of output signals U wherein each said output signal U=01 02 03+01' 02' 03'.
Claim 12
Dependent Claim
50 words
The apparatus as set forth in claim 7 wherein said logical signal T a , is toggled between a logic "0" and a logic "1" state to self-test said multiple input self-checking circuit means, said toggling and said multiple self-checking circuit means operating independently from associated triplicated logic circuitry. .
Claim 13
Dependent Claim
19 words
The apparatus as set forth in claim 8 wherein said multiple self-checking circuit comprises a multiple input OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-09 | 1993-04-10 | 1993-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-09 | 1997-04-10 | 1997-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-09 | 2001-04-10 | 2001-10-10 | $7700.00 | Window Closed / Lapsed |