US3825894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-checking parity checker for two or more independent parity coded data paths
Assignee: International Business Machines Corp
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Filing: 1973-09-24
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Granted: 1974-07-23
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Expires: 1993-09-24
Abstract
Abstract A series of self-checking error checking circuits are disclosed for checking two or more independent sets of parity coded data lines. Each data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. Each checking circuit comprises two Exclusive-OR tree circuits wherein each tree obtains its inputs from different input lines of each set of independent data lines whereby complementing outputs are produced by the two tree circuits for any correct signal set when the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.
Inventors
- 👤 A Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/007; H03K19/0075; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H03K19/20
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A self-testing error-checking circuit for checking independent parity coded binary data appearing on each of a plurality of nonoverlapping sets of data lines, said checking circuit comprising: a pair of Exclusive-OR logic trees, each tree having only one output and each having inputs selectively connected to different data lines of each set for producing a first data configuration when the parity coded data of both sets is correct and the checking circuit is producing no error and for producing a second data configuration when a single error is present in either the parity coded data sets or in the operation of the checking circuit, and means connected to said outputs for sensing said second data configuration.
Claim 2
Dependent Claim
116 words
A self-testing error-checking circuit for checking independent parity coded binary data appearing on each of a plurality of nonoverlapping sets of data lines, said checking circuit comprising: a pair of Exclusive-OR logic trees, each tree having only one output and each having inputs selectively connected to different data lines of each set for producing a first data configuration when the parity coded data of both sets is correct and the checking circuit is producing no error and for producing a second data configuration when a single error is present in either the parity coded data sets or in the operation of the checking circuit, and means connected to said outputs for sensing said second data configuration.
Claim 3
Dependent Claim
84 words
The checking circuit of claim 1 for checking two sets of nine data lines, each data line set being divided into three distinct nonoverlapping groups, one of said logic trees being connected to one of said groups of one data line set and to two of said groups of the other data line set, the other of said logIc trees being connected to the other two groups of said one data line set and to the other group of said other data line set.
Claim 4
Dependent Claim
22 words
The checking circuit of claim 2 wherein the logic trees are comprised of two-input, single output Exclusive-OR circuits and an invert circuit.
Claim 5
Dependent Claim
57 words
The checking circuit of claim 1 for checking three sets of data lines, each set being divided into three distinct nonoverlapping groups, one of said logic trees being connected to one of said groups of each data line set, the other of said logic trees being connected to the remaining two groups of each data line set.
Claim 6
Dependent Claim
18 words
The checking circuit of claim 4 wherein the logic trees are comprised of two-input, single output Exclusive-OR circuits.
Claim 7
Dependent Claim
262 words
A self-testing error checking circuit for checking two-rail parity coded binary data appearing on two independent sets of eighteen data lines, each of said data line sets being divided into three equal distinct nonoverlapping groups, said checking circuit comprising: a logic circuit means selectively connected to each group of data lines, each said logic circuit means performing the function of a three-way Exclusive-OR circuit means for producing complementary binary outputs from each of said logic circuit means, first and second additional logic circuit means each for performing a three-way Exclusive-OR function and having a plurality of inputs and a single output, means coupling the inputs of the first additional logic circuit means to the true and complement outputs of two of the logic circuit means coupled to the first data line set groups and of one of the logic circuit means coupled to the second data line set groups, and means coupling the inputs of the second additional logic circuit means to the true and complement outputs of the other two of the logic circuit means coupled to the second data line set groups and of the other one of the logic circuit means coupled to the first data line set groups, the two binary outputs from said additional two logic circuit means having a first predetermined data configuration when the parity coded binary data is correct and the checking circuit is producing no error and having a second predetermined data configuration when a single error is present in either the parity coded data or in the operation of the checking circuit.
Claim 8
Dependent Claim
262 words
A self-testing error checking circuit for checking two-rail parity coded binary data appearing on two independent sets of eighteen data lines, each of said data line sets being divided into three equal distinct nonoverlapping groups, said checking circuit comprising: a logic circuit means selectively connected to each group of data lines, each said logic circuit means performing the function of a three-way Exclusive-OR circuit means for producing complementary binary outputs from each of said logic circuit means, first and second additional logic circuit means each for performing a three-way Exclusive-OR function and having a plurality of inputs and a single output, means coupling the inputs of the first additional logic circuit means to the true and complement outputs of two of the logic circuit means coupled to the first data line set groups and of one of the logic circuit means coupled to the second data line set groups, and means coupling the inputs of the second additional logic circuit means to the true and complement outputs of the other two of the logic circuit means coupled to the second data line set groups and of the other one of the logic circuit means coupled to the first data line set groups, the two binary outputs from said additional two logic circuit means having a first predetermined data configuration when the parity coded binary data is correct and the checking circuit is producing no error and having a second predetermined data configuration when a single error is present in either the parity coded data or in the operation of the checking circuit.
Claim 9
Dependent Claim
23 words
The checking circuit of claim 6 fabricated on a single semiconductor chip, whereby only two output pins are required for the checking circuit.
Claim 10
Dependent Claim
43 words
The checking circuit of claim 7 further comprising: means external to the chip connected to said outputs of the additonal logic circuit means for sensing an error condition, said latter means possessing the characteristic of tolerating a single failure without producing an error.
References Cited (Backward Citations)
US3634662A
Cited
US3602886A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-22 | 1978-01-21 | 1978-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-22 | 1982-01-21 | 1982-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-22 | 1986-01-21 | 1986-07-23 | $7700.00 | Window Closed / Lapsed |