US3891969A
Expired / Lapsed
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Syndrome logic checker for an error correcting code decoder
Assignee: Unisys Corp
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Filing: 1974-09-03
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Granted: 1975-06-24
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Expires: 1994-09-03
Abstract
Abstract A checking circuit for the decoder of an error correcting code and a method of the designing thereof is disclosed. The method involves an algorithm that checks the syndrome generator network logic of the decoder. The syndrome checker includes a parity predict network and a parity check network in which the parity predict network is a parity tree whose terms in combination with the terms that define the syndrome generator logic meet the properties of the algorithm.
Inventors
- 👤 Bruce A Christensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/19
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
177 words
In combination with a syndrome generator network that generates syndrome bits from a vinary word that includes information bits and check bits, a syndrome checker for detecting errors in the generation of said syndrome bits from said binary word, said syndrome checker comprising: a parity predict network for generating a parity predict bit; a parity check network for generating a syndrome check bit; first means for coupling the bits of said binary word as inputs to said syndrome generator network and to said parity predict network in accordance with the following conditions: 1. each bit of the binary word appears in the syndrome generator network logic equations and the parity predict network logic equations an even number of times; 2. the output of each gate within the syndrome generator network and the parity predict network has an odd fan-out; second means coupling said syndrome bits and said parity predict bit as inputs to said parity check network for generating as an output therefrom alternative signals for indicating that said syndrome bits are either correct or not correct.
Claim 2
Dependent Claim
177 words
In combination with a syndrome generator network that generates syndrome bits from a vinary word that includes information bits and check bits, a syndrome checker for detecting errors in the generation of said syndrome bits from said binary word, said syndrome checker comprising: a parity predict network for generating a parity predict bit; a parity check network for generating a syndrome check bit; first means for coupling the bits of said binary word as inputs to said syndrome generator network and to said parity predict network in accordance with the following conditions: 1. each bit of the binary word appears in the syndrome generator network logic equations and the parity predict network logic equations an even number of times; 2. the output of each gate within the syndrome generator network and the parity predict network has an odd fan-out; second means coupling said syndrome bits and said parity predict bit as inputs to said parity check network for generating as an output therefrom alternative signals for indicating that said syndrome bits are either correct or not correct.
Claim 3
Dependent Claim
57 words
the output of each gate within the syndrome generator network and the parity predict network has an odd fan-out; second means coupling said syndrome bits and said parity predict bit as inputs to said parity check network for generating as an output therefrom alternative signals for indicating that said syndrome bits are either correct or not correct.
Claim 4
Dependent Claim
57 words
the output of each gate within the syndrome generator network and the parity predict network has an odd fan-out; second means coupling said syndrome bits and said parity predict bit as inputs to said parity check network for generating as an output therefrom alternative signals for indicating that said syndrome bits are either correct or not correct.
Claim 5
Dependent Claim
116 words
In combination with a syndrome generator network, including an overall parity network, that generates the syndrome bits SN 1, . . . SO and an overall parity bit PO from a binary word that includes information bits and check bits including a parity bit, a syndrome checker for detecting errors in the generation of said syndrome bits from said binary word, said syndrome checker comprising: a parity predict network for generating a parity predict bit L; a parity check network for generating a syndrome check bits CS; first means for coupling the bits of said binary word as inputs to said syndrome generator network and to said parity predict network in accordance with the following conditions,
Claim 6
Dependent Claim
116 words
In combination with a syndrome generator network, including an overall parity network, that generates the syndrome bits SN 1, . . . SO and an overall parity bit PO from a binary word that includes information bits and check bits including a parity bit, a syndrome checker for detecting errors in the generation of said syndrome bits from said binary word, said syndrome checker comprising: a parity predict network for generating a parity predict bit L; a parity check network for generating a syndrome check bits CS; first means for coupling the bits of said binary word as inputs to said syndrome generator network and to said parity predict network in accordance with the following conditions,
Claim 7
Dependent Claim
76 words
the output of each gate within the syndrome generator network and the parity predict network has an odd number of fan-outs; second means for coupling said overall parity bit PO, said syndrome bits SN 1, . . . SO and said parity predict bit L as inputs to said parity check network and generating the syndrome check bit CS indicaTing that said syndrome bits SN 1, . . . SO are either correct or not correct.
Claim 8
Dependent Claim
76 words
the output of each gate within the syndrome generator network and the parity predict network has an odd number of fan-outs; second means for coupling said overall parity bit PO, said syndrome bits SN 1, . . . SO and said parity predict bit L as inputs to said parity check network and generating the syndrome check bit CS indicaTing that said syndrome bits SN 1, . . . SO are either correct or not correct.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-23 | 1978-12-23 | 1979-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-23 | 1982-12-23 | 1983-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-23 | 1986-12-23 | 1987-06-24 | $7700.00 | Window Closed / Lapsed |