Patent US2115917A successfully refreshed from Google Patents.
US3784978A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-checking decoder
Assignee: AT&T Inc
•
Filing: 1973-02-14
•
Granted: 1974-01-08
•
Expires: 1993-02-14
Abstract
Abstract The self-checking decoder of the present invention includes a number of logic NAND gates arranged to process input address and parity signals in such a manner that if a fault exists in the input codes or the decoder, the decoder will either properly decode the input address or will signal the presence of the defect. In addition, if invalid code combinations are applied to the circuit on a regular or selective basis, the circuit is arranged to signal the existence of faults of which the circuit was tolerant.
Inventors
- 👤 M Zola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
A self-checking decoder for generating an output signal on one of m output lines in response to an n-tuple of address and parity signals comprising a. means for applying said n-tuple to respective first input leads and for generating the complement of said n-tuple on respective second input leads, b. m n-input AND circuits whose inputs are selectively connected to mutually exclusive combinations of n of said first and second input leads, and c. means connecting the outputs of each of said n-input AND circuits to a different one of said m output lines.
Claim 2
Dependent Claim
94 words
A self-checking decoder for generating an output signal on one of m output lines in response to an n-tuple of address and parity signals comprising a. means for applying said n-tuple to respective first input leads and for generating the complement of said n-tuple on respective second input leads, b. m n-input AND circuits whose inputs are selectively connected to mutually exclusive combinations of n of said first and second input leads, and c. means connecting the outputs of each of said n-input AND circuits to a different one of said m output lines.
Claim 3
Dependent Claim
21 words
Apparatus according to claim 1 wherein m 2n a where a > or = 1 is the number of parity signals.
Claim 4
Dependent Claim
26 words
Apparatus according to claim 2 further comprising an input decoder for generating an output signal whenever a valid n-tuple is applied to said first input leads.
Claim 5
Dependent Claim
57 words
Apparatus according to claim 3 wherein said parity signals are chosen in the absence of error to maintain the mod 2 sum of said n-tuple equal to 1 and wherein said input decoder comprises an n-input OR circuit and means for connecting the n-inputs of said OR circuit to respective ones of said n first input leads.
Claim 6
Dependent Claim
29 words
Apparatus according to claim 3 further comprising an output decoder for detecting when at least one of the output leads of said n-input AND circuits assumes a preselected condition.
Claim 7
Dependent Claim
31 words
Apparatus according to claim 5 wherein said output decoder comprises an m-input OR circuit and means for connecting the m-inputs of said OR circuit to respective ones of said output leads.
Claim 8
Dependent Claim
42 words
Apparatus according to claim 5 further comprising a. an error generator for supplying invalid n-tuples, and b. means responsive to said input and output decoder for indicating when an output on one of said output lines occurs when an invalid n-tuple occurs.
Claim 9
Dependent Claim
76 words
Apparatus according to claim 6 wherein said parity signals are chosen in the absence of error to maintain the modulo 2 sum of said n-tuple equal to 1 further comprising a. an n-input OR circuit and means for connecting the n-inputs of said n-input OR circuit to respective ones of said n first input leads, and b. a 2-input AND circuit whose inputs are connected to the output leads of said n-input and m-input OR circuits.
Claim 10
Dependent Claim
41 words
Apparatus according to claim 8 wherein each of said n-input AND circuits comprises an n-input NAND gate and an inverter whose input is connected to the output of said NAND gate and whose output is connected to a respective output line.
Claim 11
Dependent Claim
45 words
Apparatus according to claim 9 wherein said means for applying said n-tuple to respective first input leads comprises n inverters whose inputs are connected to individual ones of said second input leads and whose outputs are connected to respective ones of said first input leads.
Claim 12
Dependent Claim
17 words
Apparatus according to claim 1 comprising means for detecting when no outputs appear on said output lines.
References Cited (Backward Citations)
US3722107A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-07 | 1977-07-09 | 1978-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-07 | 1981-07-09 | 1982-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-07 | 1985-07-09 | 1986-01-08 | $7700.00 | Window Closed / Lapsed |