US6979855B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-quality praseodymium gate dielectrics
Assignee: Micron Technology Inc
•
Filing: 2004-01-27
•
Granted: 2005-12-27
•
Expires: 2024-01-27
Abstract
Abstract A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO 2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
Inventors
- 👤 Kie Y. Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:48
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; C; C23; C23C; C23C14/00; C23C14/06; C23C14/14; C23C14/16; C23C14/58; C23C14/5826; C23C14/5846; C23C14/5853; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P14/40; H10P14/6319; H10P14/6322; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69396
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
79 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer.
Claim 2
Dependent Claim
79 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer.
Claim 3
Dependent Claim
21 words
The transistor of claim 1 , wherein the surface portion of the body region is oriented in a (100) crystalline plane.
Claim 4
Dependent Claim
21 words
The transistor of claim 1 , wherein the surface portion of the body region is oriented in a (111) crystalline plane.
Claim 5
Dependent Claim
15 words
The transistor of claim 1 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 6
Dependent Claim
18 words
The transistor of claim 1 , wherein the praseodymium oxide dielectric layer is substantially without a silicon oxide.
Claim 7
Dependent Claim
21 words
The transistor of claim 1 , wherein the praseodymium oxide dielectric layer provides a gate dielectric layer substantially without a silicide.
Claim 8
Dependent Claim
106 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 dielectric layer on the surface portion of the body region, wherein the Pr 2 O 3 dielectric layer contacts the surface portion substantially without an interface material between the Pr 2 O 3 dielectric layer and the surface portion and the Pr 2 O 3 dielectric layer has a dielectric constant of about 31; and a gate on the Pr 2 O 3 dielectric layer.
Claim 9
Dependent Claim
106 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 dielectric layer on the surface portion of the body region, wherein the Pr 2 O 3 dielectric layer contacts the surface portion substantially without an interface material between the Pr 2 O 3 dielectric layer and the surface portion and the Pr 2 O 3 dielectric layer has a dielectric constant of about 31; and a gate on the Pr 2 O 3 dielectric layer.
Claim 10
Dependent Claim
21 words
The transistor of claim 7 , wherein the surface portion of the body region is oriented in a (100) crystalline plane.
Claim 11
Dependent Claim
21 words
The transistor of claim 7 , wherein the surface portion of the body region is oriented in a (111) crystalline plane.
Claim 12
Dependent Claim
17 words
The transistor of claim 7 , wherein the Pr 2 O 3 dielectric layer is substantially amorphous.
Claim 13
Dependent Claim
133 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 dielectric layer on the surface portion of the body region, wherein the Pr 2 O 3 dielectric layer contacts the surface portion substantially without an interface material between the Pr 2 O 3 dielectric layer and the surface portion; and a gate on the Pr 2 O 3 dielectric layer; the Pr 2 O 3 dielectric layer formed by a process including: evaporation depositing a praseodymium (Pr) metal layer on the body region; and oxidizing the Pr metal layer to form the Pr 2 O 3 dielectric layer on the body region.
Claim 14
Dependent Claim
133 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 dielectric layer on the surface portion of the body region, wherein the Pr 2 O 3 dielectric layer contacts the surface portion substantially without an interface material between the Pr 2 O 3 dielectric layer and the surface portion; and a gate on the Pr 2 O 3 dielectric layer; the Pr 2 O 3 dielectric layer formed by a process including: evaporation depositing a praseodymium (Pr) metal layer on the body region; and oxidizing the Pr metal layer to form the Pr 2 O 3 dielectric layer on the body region.
Claim 15
Dependent Claim
20 words
The transistor of claim 11 , wherein evaporation depositing the Pr metal layer includes evaporation depositing by electron beam evaporation.
Claim 16
Dependent Claim
24 words
The transistor of claim 11 , wherein oxidizing the Pr metal layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 17
Dependent Claim
97 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a praseodymium oxide dielectric layer on the body region, wherein the praseodymium oxide contacts the body region substantially without an interface material between the praseodymium oxide and the body region; and a gate on the praseodymium oxide dielectric layer; the praseodymium oxide dielectric layer formed by a process including: evaporation depositing a praseodymium (Pr) metal layer on the body region; and oxidizing the Pr metal layer to form the praseodymium oxide dielectric layer on the body region.
Claim 18
Dependent Claim
97 words
A transistor comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a praseodymium oxide dielectric layer on the body region, wherein the praseodymium oxide contacts the body region substantially without an interface material between the praseodymium oxide and the body region; and a gate on the praseodymium oxide dielectric layer; the praseodymium oxide dielectric layer formed by a process including: evaporation depositing a praseodymium (Pr) metal layer on the body region; and oxidizing the Pr metal layer to form the praseodymium oxide dielectric layer on the body region.
Claim 19
Dependent Claim
22 words
The transistor of claim 14 , wherein the praseodymium oxide dielectric layer has an equivalent oxide thickness of less than 2 nanometers.
Claim 20
Dependent Claim
35 words
The transistor of claim 14 , wherein evaporation depositing the Pr metal layer includes evaporation depositing by electron beam evaporation and oxidizing the Pr metal layer includes oxidizing the Pr metal layer with atomic oxygen.
Claim 21
Dependent Claim
28 words
The transistor of claim 14 , wherein the process for forming the praseodymium oxide dielectric layer includes forming the praseodymium oxide dielectric layer substantially without a silicon oxide.
Claim 22
Dependent Claim
27 words
The transistor of claim 14 , wherein the process for forming the praseodymium oxide dielectric layer includes forming the praseodymium oxide dielectric layer substantially without a silicide.
Claim 23
Dependent Claim
144 words
A memory comprising: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 24
Dependent Claim
144 words
A memory comprising: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 25
Dependent Claim
20 words
The memory of claim 19 , wherein the praseodymium oxide dielectric layer exhibits a dielectric constant (k) of approximately 31.
Claim 26
Dependent Claim
15 words
The memory of claim 19 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 27
Dependent Claim
27 words
The memory of claim 19 , wherein the praseodymium oxide dielectric layer provides a gate dielectric layer substantially without a silicon oxide and substantially without a silicide.
Claim 28
Dependent Claim
102 words
A memory comprising: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, the praseodymium oxide dielectric layer having an equivalent oxide thickness less than 2 nanometers, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer.
Claim 29
Dependent Claim
102 words
A memory comprising: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, the praseodymium oxide dielectric layer having an equivalent oxide thickness less than 2 nanometers, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer.
Claim 30
Dependent Claim
22 words
The memory of claim 23 , wherein the praseodymium oxide dielectric layer provides a gate dielectric layer substantially without a silicon oxide.
Claim 31
Dependent Claim
15 words
The memory of claim 23 , wherein the memory is a dynamic random access memory.
Claim 32
Dependent Claim
13 words
The memory of claim 23 , wherein the memory is a flash memory.
Claim 33
Dependent Claim
163 words
An information handling device comprising: a processor; a memory device including: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 34
Dependent Claim
163 words
An information handling device comprising: a processor; a memory device including: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 35
Dependent Claim
22 words
The information handling device of claim 27 , wherein the praseodymium oxide dielectric layer exhibits a dielectric constant (k) of approximately 31.
Claim 36
Dependent Claim
17 words
The information handling device of claim 27 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 37
Dependent Claim
15 words
The information handling device of claim 27 , wherein the information handling includes a computer.
Claim 38
Dependent Claim
121 words
An information handling device comprising: a processor; a memory device including: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, the praseodymium oxide dielectric layer having an equivalent oxide thickness less than 2 nanometers, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; and a system bus coupling the processor to the memory device.
Claim 39
Dependent Claim
121 words
An information handling device comprising: a processor; a memory device including: a number of access transistors, each access transistor including: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer on the surface portion of the body region, the praseodymium oxide dielectric layer having an equivalent oxide thickness less than 2 nanometers, wherein the praseodymium oxide contacts the surface portion substantially without an interface material between the praseodymium oxide and the surface portion; and a gate on the praseodymium oxide dielectric layer; and a system bus coupling the processor to the memory device.
Claim 40
Dependent Claim
24 words
The information handling device of claim 31 , wherein the praseodymium oxide dielectric layer provides a gate dielectric layer substantially without a silicon oxide.
Claim 41
Dependent Claim
16 words
The information handling device of claim 31 , wherein the memory device is a flash memory.
Claim 42
Dependent Claim
16 words
The information handling device of claim 31 , wherein the information handling system includes a computer.
References Cited (Backward Citations)
US4058430A
Cited
US4215156A
Cited
US4333808A
Cited
US4399424A
Cited
US4647947A
Cited
US4920071A
Cited
US4767641A
Cited
US5840897A
Cited
EP0540993A1
Cited
US5810923A
Cited
US5828080A
Cited
US5822256A
Cited
US5625233A
Cited
US5751021A
Cited
US5801105A
Cited
US5795808A
Cited
US6154280A
Cited
US6387712B1
Cited
US6258637B1
Cited
US5698022A
Cited
US6652924B2
Cited
US6010969A
Cited
US6217645B1
Cited
US6013553A
Cited
US6020024A
Cited
US5912797A
Cited
US6025627A
Cited
US6331465B1
Cited
US6294813B1
Cited
US6225168B1
Cited
US6027961A
Cited
US6391769B1
Cited
US6225237B1
Cited
US6211035B1
Cited
US6544875B1
Cited
US20010002280A1
Cited
US6171900B1
Cited
US6273951B1
Cited
US6297539B1
Cited
US6632279B1
Cited
US20040007171A1
Cited
US6458701B1
Cited
US6541079B1
Cited
US6780704B1
Cited
US6831315B2
Cited
US6638859B2
Cited
US6303481B2
Cited
US6531354B2
Cited
US6527866B1
Cited
US6627503B2
Cited
US20010030352A1
Cited
US6699747B2
Cited
US6537613B1
Cited
US6777353B2
Cited
JP2001332546A
Cited
US6821862B2
Cited
US20020001971A1
Cited
US6551929B1
Cited
US6592942B1
Cited
US6521911B2
Cited
US20030193061A1
Cited
US20020094632A1
Cited
US6518634B1
Cited
US6465334B1
Cited
US6300203B1
Cited
US6660660B2
Cited
US6368941B1
Cited
US20020068466A1
Cited
US20020089023A1
Cited
US6713846B1
Cited
US20030104666A1
Cited
US6608378B2
Cited
US20020111001A1
Cited
US6495436B2
Cited
US20030003702A1
Cited
US6586792B2
Cited
US6448192B1
Cited
US6514828B2
Cited
US20020155689A1
Cited
US20020155688A1
Cited
US6661058B2
Cited
US6787413B2
Cited
US20050037563A1
Cited
US20020192979A1
Cited
US20020192974A1
Cited
US20020192975A1
Cited
US6709989B2
Cited
US20030017717A1
Cited
US6534420B2
Cited
US20030042526A1
Cited
US20030052358A1
Cited
US6461914B1
Cited
US6639267B2
Cited
US20030045060A1
Cited
US6573199B2
Cited
US20050026349A1
Cited
US6844203B2
Cited
US20030045078A1
Cited
US20050029605A1
Cited
US6730575B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-12-26 | 2009-06-27 | 2009-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-12-26 | 2013-06-27 | 2013-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-12-26 | 2017-06-27 | 2017-12-27 | $7700.00 | Window Closed / Lapsed |