US6661058B2
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US
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Highly reliable gate oxide and method of fabrication
Assignee: Micron Technology Inc
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Filing: 2002-02-11
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Granted: 2003-12-09
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Expires: 2022-02-11
Abstract
Abstract An ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) and a method of formation are disclosed. The ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) is formed by a two-step process. A thin hafnium (Hf) film is first formed by thermal evaporation at a low substrate temperature, after which the thin hafnium film is radically oxidized using a krypton/oxygen (Kr/O 2 ) high-density plasma to form the ultra-thin gate oxide layer of hafnium oxide (HfO 2 ). The ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) formed by the method of the present invention is thermally stable in contact with silicon and is resistive to impurity diffusion at the HfO 2 /silicon interface. The formation of the ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) eliminates the need for a diffusion barrier layer, allows thickness uniformity of the field oxide on the isolation regions and, more importantly, preserves the atomically smooth surface of the silicon substrate.
Inventors
- 👤 Kie Y. Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:58
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; H10P14/6319; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69392
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
63 words
A transistor comprising: source and drain regions provided in a semiconductor substrate; and a gate structure on said semiconductor substrate between said source and drain regions, said gate structure comprising a hafnium oxide layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer, wherein said hafnium oxide layer preserves the atomically smooth surface of said semiconductor substrate.
Claim 2
Dependent Claim
63 words
A transistor comprising: source and drain regions provided in a semiconductor substrate; and a gate structure on said semiconductor substrate between said source and drain regions, said gate structure comprising a hafnium oxide layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer, wherein said hafnium oxide layer preserves the atomically smooth surface of said semiconductor substrate.
Claim 3
Dependent Claim
22 words
The transistor of claim 1 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 100 Angstroms.
Claim 4
Dependent Claim
22 words
The transistor of claim 2 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 50 Angstroms.
Claim 5
Dependent Claim
28 words
The transistor of claim 1 , wherein said conductive layer is formed of a material selected from the group consisting of metals, metal silicides, polysilicon and metal oxides.
Claim 6
Dependent Claim
14 words
The transistor of claim 1 , wherein said semiconductor substrate is a silicon substrate.
Claim 7
Dependent Claim
27 words
The transistor of claim 5 , wherein said silicon substrate has a surface of < 100 > orientation, said surface being adjacent to said hafnium oxide layer.
Claim 8
Dependent Claim
27 words
The transistor of claim 5 , wherein said silicon substrate has a surface of < 111 > orientation, said surface being adjacent to said hafnium oxide layer.
Claim 9
Dependent Claim
14 words
The transistor of claim 1 further comprising a silicide layer overlying said conductive layer.
Claim 10
Dependent Claim
74 words
A memory device comprising: a semiconductor substrate; a memory cell access transistor comprising: a gate stack fabricated on said semiconductor substrate, said gate stack including a hafnium oxide layer overlying said semiconductor substrate and a conductive layer overlying said hafnium oxide layer, wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 100 Angstroms; and source and drain regions formed in said semiconductor substrate disposed adjacent to said gate stack.
Claim 11
Dependent Claim
74 words
A memory device comprising: a semiconductor substrate; a memory cell access transistor comprising: a gate stack fabricated on said semiconductor substrate, said gate stack including a hafnium oxide layer overlying said semiconductor substrate and a conductive layer overlying said hafnium oxide layer, wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 100 Angstroms; and source and drain regions formed in said semiconductor substrate disposed adjacent to said gate stack.
Claim 12
Dependent Claim
23 words
The memory device of claim 9 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 50 Angstroms.
Claim 13
Dependent Claim
29 words
The memory device of claim 9 , wherein said conductive layer is formed of a material selected from the group consisting of metals, metal silicides, polysilicon and metal oxides.
Claim 14
Dependent Claim
15 words
The memory device of claim 9 , wherein said semiconductor substrate is a silicon substrate.
Claim 15
Dependent Claim
28 words
The memory device of claim 12 , wherein said silicon substrate has a surface of < 100 > orientation, said surface being adjacent to said hafnium oxide layer.
Claim 16
Dependent Claim
28 words
The memory device of claim 12 , wherein said silicon substrate has a surface of < 111 > orientation, said surface being adjacent to said hafnium oxide layer.
Claim 17
Dependent Claim
15 words
The memory device of claim 9 further comprising a silicide layer overlying said conductive layer.
Claim 18
Dependent Claim
94 words
A processor-based system comprising: a processor; and an integrated circuit coupled to said processor, at least one of said integrated circuit and processor comprising a transistor, said transistor comprising: source and drain regions provided in a silicon substrate; and a gate stack fabricated on said silicon substrate, said gate stack including a hafnium oxide layer in contact with said silicon substrate, wherein at least a portion of said silicon substrate in contact with said hafnium oxide layer has a surface of < 111 > orientation, and a conductive layer overlying said hafnium oxide layer.
Claim 19
Dependent Claim
94 words
A processor-based system comprising: a processor; and an integrated circuit coupled to said processor, at least one of said integrated circuit and processor comprising a transistor, said transistor comprising: source and drain regions provided in a silicon substrate; and a gate stack fabricated on said silicon substrate, said gate stack including a hafnium oxide layer in contact with said silicon substrate, wherein at least a portion of said silicon substrate in contact with said hafnium oxide layer has a surface of < 111 > orientation, and a conductive layer overlying said hafnium oxide layer.
Claim 20
Dependent Claim
23 words
The processor-based system of claim 16 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 100 Angstroms.
Claim 21
Dependent Claim
23 words
The processor-based system of claim 17 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 50 Angstroms.
Claim 22
Dependent Claim
29 words
The processor-based system of claim 16 , wherein said conductive layer is formed of a material selected from the group consisting of metals, metal silicides, polysilicon and metal oxides.
Claim 23
Dependent Claim
36 words
The processor-based system of claim 16 , wherein a second portion of said silicon substrate has a surface of < 100 > orientation, said surface of said second portion being adjacent to said hafnium oxide layer.
Claim 24
Dependent Claim
16 words
The processor-based system of claim 16 , further comprising a silicide layer overlying said conductive layer.
Claim 25
Dependent Claim
46 words
A gate structure for a semiconductor device comprising: a hafnium oxide layer in contact with a semiconductor substrate, said hafnium oxide layer being formed by forming a hafnium layer on said substrate and oxidizing said hafnium layer; and a conductive layer over said hafnium oxide layer.
Claim 26
Dependent Claim
46 words
A gate structure for a semiconductor device comprising: a hafnium oxide layer in contact with a semiconductor substrate, said hafnium oxide layer being formed by forming a hafnium layer on said substrate and oxidizing said hafnium layer; and a conductive layer over said hafnium oxide layer.
Claim 27
Dependent Claim
22 words
The transistor of claim 22 , wherein said hafnium oxide layer has a thickness of about 10 Angstroms to about 100 Angstroms.
Claim 28
Dependent Claim
14 words
The transistor of claim 22 , wherein said semiconductor substrate is a silicon substrate.
Claim 29
Dependent Claim
32 words
The transistor of claim 24 , wherein at least a portion of said silicon substrate has a surface of < 111 > orientation, said surface being adjacent to said hafnium oxide layer.
Claim 30
Dependent Claim
29 words
The gate structure of claim 22 , wherein said conductive layer is formed of a material selected from the group consisting of metals, metal silicides, polysilicon and metal oxides.
Claim 31
Dependent Claim
51 words
A transistor comprising: source and drain regions provided in a semiconductor substrate; and a gate structure on said semiconductor substrate between said source and drain regions, said gate structure comprising a hafnium krypton plasma oxidized layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer.
Claim 32
Dependent Claim
51 words
A transistor comprising: source and drain regions provided in a semiconductor substrate; and a gate structure on said semiconductor substrate between said source and drain regions, said gate structure comprising a hafnium krypton plasma oxidized layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer.
Claim 33
Dependent Claim
22 words
The transistor of claim 27 , wherein said oxidized hafnium layer has a thickness of about 10 Angstroms to about 100 Angstroms.
Claim 34
Dependent Claim
14 words
The transistor of claim 27 , wherein said semiconductor substrate is a silicon substrate.
Claim 35
Dependent Claim
32 words
The transistor of claim 29 , wherein at least a portion of said silicon substrate has a surface of < 111 > orientation, said surface being adjacent to said oxidized hafnium layer.
Claim 36
Dependent Claim
14 words
The transistor of claim 27 further comprising a silicide layer overlying said conductive layer.
Claim 37
Dependent Claim
28 words
The transistor of claim 27 , wherein said conductive layer is formed of a material selected from the group consisting of metals, metal silicides, polysilicon and metal oxides.
Claim 38
Dependent Claim
63 words
A memory device comprising: a semiconductor substrate; a memory cell access transistor comprising: a gate stack fabricated on said semiconductor substrate, said gate structure comprising a oxidized thermally evaporated hafnium oxide layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer; and source and drain regions formed in said semiconductor substrate disposed adjacent to said gate stack.
Claim 39
Dependent Claim
63 words
A memory device comprising: a semiconductor substrate; a memory cell access transistor comprising: a gate stack fabricated on said semiconductor substrate, said gate structure comprising a oxidized thermally evaporated hafnium oxide layer in contact with said semiconductor substrate and a conductive layer overlying said hafnium oxide layer; and source and drain regions formed in said semiconductor substrate disposed adjacent to said gate stack.
Claim 40
Dependent Claim
23 words
The memory device of claim 33 , wherein said oxidized hafnium layer has a thickness of about 10 Angstroms to about 100 Angstroms.
Claim 41
Dependent Claim
42 words
The memory device of claim 33 , wherein said semiconductor substrate is a silicon substrate, and wherein at least a portion of a surface of said substrate in contact with said oxidized hafnium layer has a surface of < 111 > orientation.
Claim 42
Dependent Claim
15 words
The memory device of claim 33 further comprising a silicide layer overlying said conductive layer.
References Cited (Backward Citations)
US6087243A
Cited
US6153538A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-12-08 | 2007-06-09 | 2007-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-12-08 | 2011-06-09 | 2011-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-12-08 | 2015-06-09 | 2015-12-09 | $7700.00 | Window Closed / Lapsed |