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US6087243A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming trench isolation with high integrity, ultra thin gate oxide

Assignee: Advanced Micro Devices Inc
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Filing: 1997-10-21
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Granted: 2000-07-11
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Expires: 2017-10-21
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Abstract

Abstract The quality of an ultra thin gate oxide film, particularly at the edges of a shallow trench isolation structure, is improved employing a double sacrificial oxide technique. After trench filling and planarization, the pad oxide layer thickness is increased during trench fill densification in an oxidizing atmosphere. The pad oxide is then removed exposing the substrate surface and trench edges. A second sacrificial oxide is formed consuming part of the substrate surface. The second sacrificial oxide is then removed along with defects in the substrate surface prior to gate oxide and gate electrode formation.

Inventors

  • 👤 Larry Yu Wang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 00:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0151; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S438/00; Y10S438/911

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 246 words
A method of manufacturing a semiconductor device having an active region isolated by an insulated trench, which method comprises: forming a first oxide layer, having a first thickness, on a main surface of a semiconductor substrate or on a main surface of an epitaxial layer formed on the semiconductor substrate; depositing a silicon nitride layer on the first oxide layer; forming a trench in the semiconductor substrate or epitaxial layer, wherein the trench has edges at the main surface; growing an oxide liner in the trench; filling the trench with insulating material; planarizing the main surface to expose the silicon nitride layer; removing the silicon nitride layer; heating at a first temperature for a first period of time, to densify the insulating material filling the trench; removing the first oxide layer, thereby exposing the main surface and the trench edges; heating in an oxidizing atmosphere, at a second temperature for a second period of time, to form a second oxide layer having a third thickness on the main surface and the trench edges; removing the second oxide layer, exposing the main surface and the trench edges; forming a gate oxide layer on the main surface and the trench edges; forming a conductive layer on the gate oxide layer; and patterning to form a gate electrode, wherein the thickness of the first oxide layer is increased to a second thickness during heating at a first temperature for a first period of time by providing an oxidizing atmosphere.
Claim 2
Independent Claim 246 words
A method of manufacturing a semiconductor device having an active region isolated by an insulated trench, which method comprises: forming a first oxide layer, having a first thickness, on a main surface of a semiconductor substrate or on a main surface of an epitaxial layer formed on the semiconductor substrate; depositing a silicon nitride layer on the first oxide layer; forming a trench in the semiconductor substrate or epitaxial layer, wherein the trench has edges at the main surface; growing an oxide liner in the trench; filling the trench with insulating material; planarizing the main surface to expose the silicon nitride layer; removing the silicon nitride layer; heating at a first temperature for a first period of time, to densify the insulating material filling the trench; removing the first oxide layer, thereby exposing the main surface and the trench edges; heating in an oxidizing atmosphere, at a second temperature for a second period of time, to form a second oxide layer having a third thickness on the main surface and the trench edges; removing the second oxide layer, exposing the main surface and the trench edges; forming a gate oxide layer on the main surface and the trench edges; forming a conductive layer on the gate oxide layer; and patterning to form a gate electrode, wherein the thickness of the first oxide layer is increased to a second thickness during heating at a first temperature for a first period of time by providing an oxidizing atmosphere.
Claim 3
Dependent Claim 35 words
The method according to claim 1, wherein: the third thickness is less than the second thickness; the second temperature is less than the first temperature; and the second time is less than the first time.
Claim 4
Dependent Claim 73 words
The method according to claim 2, wherein: the third thickness is about 100 Å to about 300 Å; the second thickness is 200 Å to about 500 Å; the second temperature is about 800° C. to about 1,000° C.; the second time is about 2 minutes to about 10 minutes; the first temperature is about 900° C. to about 1,100° C.; and the first time is about 2 hours to about 3 hours.
Claim 5
Dependent Claim 18 words
The method according to claim 3, wherein the first thickness is about 100 Å to about 300 Å.
Claim 6
Dependent Claim 42 words
The method according to claim 2, wherein the insulating material comprises silicon dioxide derived from tetraethyl orthosilicate deposited by low pressure chemical vapor deposition, silicon dioxide derived from silane deposited by low pressure chemical vapor deposition, or a high density plasma oxide.
Claim 7
Dependent Claim 24 words
The method according to claim 5, wherein the insulating material comprises silicon dioxide derived from tetraethyl orthosilicate deposited by low pressure chemical vapor deposition.
Claim 8
Dependent Claim 16 words
The method according to claim 2, comprising removing the first and second oxide layers by etching.
Claim 9
Dependent Claim 11 words
The method according to claim 7, comprising etching using hydrofluoric acid.
Claim 10
Dependent Claim 31 words
The method according to claim 2, further comprising ion implanting impurities to form retrograde well implants after planarizing, wherein heating at the first temperature effects activation of the retrograde well implants.
Claim 11
Dependent Claim 20 words
The method according to claim 7, comprising cleaning the main surface prior to etching the first and second oxide layers.
Claim 12
Dependent Claim 17 words
The method according to claim 10, comprising cleaning using hydrogen peroxide or hydrogen peroxide and ammonium hydroxide.
Claim 13
Dependent Claim 14 words
The method according to claim 2, wherein the conductive layer comprises doped polycrystalline silicon.
Claim 14
Dependent Claim 15 words
The method according to claim 2, further comprising ion implanting impurities to form source/drain regions.
Claim 15
Dependent Claim 19 words
The method according to claim 2, comprising forming the gate oxide layer by thermal oxidation or chemical vapor deposition.
Claim 16
Dependent Claim 31 words
The method according to claim 1, further comprising: forming a nitride layer on the first oxide layer before forming the trench; and removing the nitride layer after planarizing the main surface.
Claim 17
Independent Claim 325 words
A method of manufacturing a semiconductor device having an active region isolated; by an insulated trench which method comprises: forming a first oxide layer, having a first thickness, on a main surface of a semiconductor substrate or on a main surface of an epitaxial layer formed on the semiconductor substrate; forming a nitride layer on the first oxide layer; etching through the nitride layer and first oxide layer to form a trench in the semiconductor substrate or epitaxial layer, wherein the trench has edges at the main surface; thermally growing an oxide liner in the trench; filling the trench with silicon oxide derived from tetraethyl orthosilicate deposited by low pressure chemical vapor deposition; planarizing the main surface by chemical-mechanical polishing; removing the nitride layer; ion implanting impurities to form retrograde well implants; heating at a first temperature for a first period of time, to densify the silicon dioxide filling the trench and to activate the retrograde well implants; cleaning the main surface; etching, using aqueous hydrofluoric acid, to remove the first oxide layer exposing the main surface and the trench edges; heating in an oxidizing atmosphere, at a second temperature less than the first temperature and for a second period of time less than the first period of time, to form a second oxide layer having a third thickness less than the second thickness on the main surface and the trench edges; cleaning the main surface; etching, employing aqueous hydrofluoric acid, to remove the second oxide layer exposing the main surface and the trench edges; forming a gate oxide layer on the main surface and the trench edges by thermal oxidation or chemical vapor deposition; forming a layer of doped polycrystalline silicon on the gate oxide layer; and etching to form a gate electrode, wherein the thickness of the first oxide layer is increased to a second thickness during heating at the first temperature for the first period of time by providing an oxidizing environment.
Claim 18
Independent Claim 325 words
A method of manufacturing a semiconductor device having an active region isolated; by an insulated trench which method comprises: forming a first oxide layer, having a first thickness, on a main surface of a semiconductor substrate or on a main surface of an epitaxial layer formed on the semiconductor substrate; forming a nitride layer on the first oxide layer; etching through the nitride layer and first oxide layer to form a trench in the semiconductor substrate or epitaxial layer, wherein the trench has edges at the main surface; thermally growing an oxide liner in the trench; filling the trench with silicon oxide derived from tetraethyl orthosilicate deposited by low pressure chemical vapor deposition; planarizing the main surface by chemical-mechanical polishing; removing the nitride layer; ion implanting impurities to form retrograde well implants; heating at a first temperature for a first period of time, to densify the silicon dioxide filling the trench and to activate the retrograde well implants; cleaning the main surface; etching, using aqueous hydrofluoric acid, to remove the first oxide layer exposing the main surface and the trench edges; heating in an oxidizing atmosphere, at a second temperature less than the first temperature and for a second period of time less than the first period of time, to form a second oxide layer having a third thickness less than the second thickness on the main surface and the trench edges; cleaning the main surface; etching, employing aqueous hydrofluoric acid, to remove the second oxide layer exposing the main surface and the trench edges; forming a gate oxide layer on the main surface and the trench edges by thermal oxidation or chemical vapor deposition; forming a layer of doped polycrystalline silicon on the gate oxide layer; and etching to form a gate electrode, wherein the thickness of the first oxide layer is increased to a second thickness during heating at the first temperature for the first period of time by providing an oxidizing environment.
Claim 19
Dependent Claim 75 words
The method according to claim 16, wherein: the third thickness about 100 Å to about 300 Å; the second thickness is about 200 Å to about 500 Å; the second temperature is about 800° C. to about 1,000° C.; the second time is about 2 minutes to about 10 minutes; the first temperature is about is about 900° C. to about 1,100° C.; and the first time is about 2 hours to about 3 hours.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-07-11 2004-01-10 2004-07-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-07-11 2008-01-10 2008-07-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-07-11 2012-01-10 2012-07-11 $7700.00 Window Closed / Lapsed

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