US5885883A
Expired / Lapsed
US
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Methods of forming trench-based isolation regions with reduced susceptibility to edge defects
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-04-15
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Granted: 1999-03-23
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Expires: 2017-04-15
Abstract
Abstract Methods of forming trench-based isolation regions with reduced susceptibility to edge defects include the steps of forming trenches at a face of a semiconductor substrate and then filling the trenches with electrically insulating regions. However, to prevent exposure of those portions of the substrate extending adjacent the trenches, supplemental oxide regions are formed at the interfaces between the upper portions of the trench sidewalls and the electrically insulating regions in the trenches, by exposing the electrically insulating regions to an oxidation atmosphere at a temperature in a range between about 950° C. and 1100° C. In particular, the supplemental oxide regions are formed as thermal oxides of higher density than the electrically insulating regions in the trenches. Thus, the supplemental oxide regions are more resistant to chemical etchants. Accordingly, when the electrically insulating regions are planarized and etched during back end processing steps, the supplemental oxide regions will not be entirely etched and, therefore, those portions of the substrate (i.e., active regions) extending adjacent the trenches will not be exposed.
Inventors
- 👤 Moon-han Park
- 👤 Yu-gyun Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:34
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
80 words
A method of forming an electrical isolation region in a semiconductor substrate, comprising the steps of: forming a trench in a first face of a semiconductor substrate; filling the trench with an electrically insulating region; and then forming a supplemental oxide region having a thickness in a range between about 100 Å and 500 Å at an interface between a sidewall of the trench and the electrically insulating region by exposing the electrically insulating region to an oxygen containing atmosphere.
Claim 2
Independent Claim
80 words
A method of forming an electrical isolation region in a semiconductor substrate, comprising the steps of: forming a trench in a first face of a semiconductor substrate; filling the trench with an electrically insulating region; and then forming a supplemental oxide region having a thickness in a range between about 100 Å and 500 Å at an interface between a sidewall of the trench and the electrically insulating region by exposing the electrically insulating region to an oxygen containing atmosphere.
Claim 3
Dependent Claim
38 words
The method of claim 1, wherein said step of forming a supplemental oxide region comprises exposing the electrically insulating region to an oxygen containing atmosphere at a temperature in a range between about 950° C. and 1100° C.
Claim 4
Dependent Claim
50 words
The method of claim 2, wherein said step of filling the trench comprises filling the trench with an electrically insulating region having a first density; and wherein said step of forming a supplemental oxide region comprises forming a supplemental oxide region having a second density greater than the first density.
Claim 5
Dependent Claim
50 words
The method of claim 1, wherein said step of filling the trench comprises filling the trench with an electrically insulating region having a first density; and wherein said step of forming a supplemental oxide region comprises forming a supplemental oxide region having a second density greater than the first density.
Claim 6
Dependent Claim
65 words
The method of claim 1, wherein said trench forming step comprises the steps of: forming an etching stop layer on the face of the substrate; patterning the etching stop layer to expose a portion of the face of the substrate; and etching the exposed portion of the face of the substrate to define the trench, using the patterned etching stop layer as an etching mask.
Claim 7
Dependent Claim
34 words
The method of claim 5, wherein said step of forming a supplemental oxide region is preceded by the step of planarizing the electrically insulating region using the etching stop layer as a etching stop.
Claim 8
Dependent Claim
65 words
The method of claim 2, wherein said trench forming step comprises the steps of: forming an etching stop layer on the face of the substrate; patterning the etching stop layer to expose a portion of the face of the substrate; and etching the exposed portion of the face of the substrate to define the trench, using the patterned etching stop layer as an etching mask.
Claim 9
Dependent Claim
34 words
The method of claim 7, wherein said step of forming a supplemental oxide region is preceded by the step of planarizing the electrically insulating region using the etching stop layer as a etching stop.
Claim 10
Dependent Claim
22 words
The method of claim 8, wherein said planarizing step comprises planarizing the electrically insulating region by chemically-mechanically polishing the electrically insulating region.
Claim 11
Dependent Claim
36 words
The method of claim 1, wherein said step of filling the trench with an electrically insulating region is preceded by the step of thermally oxidizing the sidewall of the trench to form a buffer layer thereon.
Claim 12
Dependent Claim
42 words
The method of claim 10, wherein said step of thermally oxidizing the sidewall of the trench comprises thermally oxidizing the sidewall of the trench to form a buffer layer having a thickness in a range between about 500 Å and 1000 Å.
Claim 13
Dependent Claim
25 words
The method of claim 11, wherein said step of filling the trench with an electrically insulating region comprises depositing an oxide layer into the trench.
Claim 14
Independent Claim
112 words
A method of forming an electrical isolation region in a semiconductor substrate, comprising the steps of: forming a trench in a first face of a semiconductor substrate; filling the trench with an electrically insulating region having a first density; then etching the electrically insulating region; and then forming a supplemental oxide region having a thickness in a range between about 100 Å and 500 Å and having a second density greater than the first density, at an interface between a sidewall of the trench and the electrically insulating region, by exposing the electrically insulating region to an oxidizing atmosphere having a temperature in a range between about 950° C. and 1100° C.
Claim 15
Independent Claim
112 words
A method of forming an electrical isolation region in a semiconductor substrate, comprising the steps of: forming a trench in a first face of a semiconductor substrate; filling the trench with an electrically insulating region having a first density; then etching the electrically insulating region; and then forming a supplemental oxide region having a thickness in a range between about 100 Å and 500 Å and having a second density greater than the first density, at an interface between a sidewall of the trench and the electrically insulating region, by exposing the electrically insulating region to an oxidizing atmosphere having a temperature in a range between about 950° C. and 1100° C.
Claim 16
Dependent Claim
79 words
The method of claim 13, wherein said step of forming a trench is preceded by the step of forming a pad oxide layer on the first face of the semiconductor substrate; and wherein said step of forming a supplemental oxide region comprises forming a supplemental oxide region at a first interface between a sidewall of the trench and the electrically insulating region and at a second interface between the first face of the substrate and the pad oxide layer.
Claim 17
Dependent Claim
34 words
The method of claim 13, wherein said step of filling the trench with an electrically insulating region comprises thermally oxidizing a sidewall of the trench and then depositing an isolation oxide into the trench.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |