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US5447884A Expired / Lapsed US ⏱️ 0.0 years remaining

Shallow trench isolation with thin nitride liner

Assignee: Qimonda AG
•
Filing: 1994-06-29
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Granted: 1995-09-05
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Expires: 2014-06-29
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Abstract

Abstract A method of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits solves a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5 nm. A densification step of a pyrogenic oxide anneal at 800° C. not only drives out impurities and achieves the same density as a conventional argon anneal at 1000° C., but also drastically reduces the thermal load.

Inventors

  • 👤 Paul M. Fahey
  • 👤 Erwin Hammerl
  • 👤 Herbert L. Ho
  • 👤 Mutsuo Morikado

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 14:24
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/05

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 138 words
A method of forming isolation members embedded in a silicon layer of an integrated circuit comprising the steps of: depositing a protective layer containing at least one layer of nitride on a top surface of a silicon layer; etching through said protective layer to form a set of isolation mask apertures; etching through said set of isolation mask apertures in a reactive ion etch process to form a set of isolation trenches; depositing a conformal layer of nitride having a thickness less than 5 nm; depositing a CVD layer of oxide having a thickness sufficient to fill said set of isolation trenches; removing that portion of said CVD layer of oxide outside said set of isolation trenches to expose said at least one layer of nitride; and stripping said at least one layer of nitride in phosphoric acid.
Claim 2
Independent Claim 138 words
A method of forming isolation members embedded in a silicon layer of an integrated circuit comprising the steps of: depositing a protective layer containing at least one layer of nitride on a top surface of a silicon layer; etching through said protective layer to form a set of isolation mask apertures; etching through said set of isolation mask apertures in a reactive ion etch process to form a set of isolation trenches; depositing a conformal layer of nitride having a thickness less than 5 nm; depositing a CVD layer of oxide having a thickness sufficient to fill said set of isolation trenches; removing that portion of said CVD layer of oxide outside said set of isolation trenches to expose said at least one layer of nitride; and stripping said at least one layer of nitride in phosphoric acid.
Claim 3
Dependent Claim 31 words
A method according to claim 1, in which said step of filling said trench is followed by a step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal.
Claim 4
Dependent Claim 45 words
A method according to claim 2, in which said step of filling said trench comprises ozone-assisted deposition of TEOS and in which said step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal drives out fluorine from said CVD layer of oxide.
Claim 5
Dependent Claim 24 words
A method according to claim 1, in which said step of filling said trench is conducted at a temperature of less than 800° C.
Claim 6
Dependent Claim 31 words
A method according to claim 4, in which said step of filling said trench is followed by a step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal.
Claim 7
Dependent Claim 45 words
A method according to claim 5, in which said step of filling said trench comprises ozone-assisted deposition of TEOS and in which said step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal drives out fluorine from said CVD layer of oxide.
Claim 8
Dependent Claim 30 words
A method according to claim 1, in which said step of depositing a conformal layer of nitride is preceded by a step of growing a thin layer of thermal oxide.
Claim 9
Dependent Claim 31 words
A method according to claim 7, in which said step of filling said trench is followed by a step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal.
Claim 10
Dependent Claim 45 words
A method according to claim 8, in which said step of filling said trench comprises ozone-assisted deposition of TEOS and in which said step of annealing said CVD layer of oxide in a pyrogenic oxidation anneal drives out fluorine from said CVD layer of oxide.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-09-04 1999-03-06 1999-09-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-09-04 2003-03-06 2003-09-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-09-04 2007-03-06 2007-09-05 $7700.00 Window Closed / Lapsed

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