Double well substrate plate trench DRAM cell array

Claim 1

A dynamic random access memory device comprising: a semiconductor substrate having a first region of a first conductivity type; at least one array of dynamic memory cells, each cell comprising an access transistor coupled to a storage capacitor, the transistors of each memory cell being formed within a second region of said semiconductor substrate, each access transistor having a control electrode, a data line contact, a storage node, and a channel region; a plurality of signal storage capacitors formed in a plurality of trenches formed in said substrate, each capacitor including a signal storage node and a reference voltage node separated by a dielectric insulator, the reference node being connected to said substrate and the storage node of each capacitor being connected to a corresponding storage node of one of said access transistors; means for physically and electrically isolating all of the channel regions of said access transistors within said one array from said first region of said substrate, said means comprising a third region of opposite conductivity type to said first region, said third region formed between between said first and second regions, said third region intersecting all of said trenches; said third region comprising a doped well formed in said substrate wherein the doped well extends beyond and below said second region and having a depth within said substrate less than that of said trenches; and means for biasing said first, second and third regions of said substrate to first, second and third different reference voltages.