US4944682A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming borderless contacts
Assignee: International Business Machines Corp
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Filing: 1989-12-21
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Granted: 1990-07-31
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Expires: 2009-12-21
Abstract
Abstract A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material, preferably an electrical conducting material, which also preferably covers additional electrical conducting or semi-conducting regions. Thereafter, all the regions are subjected to the given etchant, but only those regions having the passivating material not covered with the etch resistant material are removed. Preferably, at this point, a layer of conducting material is deposited over all the regions.
Inventors
- 👤 John E. Cronin
- 👤 Susan F. Cronin
- 👤 Carter W. Kaanta
- 👤 Charles W. Koburger, III
- 👤 Stephen E. Luce
- 👤 Dale J. Pearson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:41
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
84 words
In the process of forming semiconductor components on a substrate material, and wherein there are at least two exposed regions having an overlying passivating material which is subject to etching by a given etchant, the improvement comprising; selectively depositing in at least a portion of a selected one but less than all of said exposed regions a material that resists said etchant, and thereafter exposing all of the regions to said etchant, whereby only said regions without said etch resisting material will be etched.
Claim 2
Dependent Claim
84 words
In the process of forming semiconductor components on a substrate material, and wherein there are at least two exposed regions having an overlying passivating material which is subject to etching by a given etchant, the improvement comprising; selectively depositing in at least a portion of a selected one but less than all of said exposed regions a material that resists said etchant, and thereafter exposing all of the regions to said etchant, whereby only said regions without said etch resisting material will be etched.
Claim 3
Dependent Claim
27 words
The invention as defined in claim 1, wherein said etch resisting material is selectively grown to cover said portion of said selected one of said exposed regions.
Claim 4
Dependent Claim
89 words
The invention as defined in claim 2, wherein the regions which are covered with said etch resisting material include a second material which differs from passivating material, and which second material supports the growth of said etch resisting material and said passivating material resists the growth of said etch resisting material, and wherein said etch resisting material is grown only in each region which has said second material and regions which have said passivating material and said second material and said etch resisting material covers both of said regions.
Claim 5
Dependent Claim
21 words
The invention as defined in claim 3, wherein said passivating material is an insulator and said second material is a semi-conductor.
Claim 6
Dependent Claim
16 words
The invention as defined in claim 4 wherein the passivating layer is a deposited capping layer.
Claim 7
Dependent Claim
16 words
The invention as defined in claim 4 wherein the passivating layer is a thermally grown oxide.
Claim 8
Dependent Claim
13 words
The invention as defined in claim 5 wherein the semi-conductor is doped silicon.
Claim 9
Dependent Claim
17 words
The invention as defined in claim 7, wherein the etch resisting material is a selectively grown metal.
Claim 10
Dependent Claim
12 words
The invention as defined in claim 8, wherein the metal is tungsten.
Claim 11
Dependent Claim
163 words
A process for forming borderless contacts on a semiconductor substrate having a plurality of gate electrodes disposed on an exposed surface thereof, each of the plurality of gate electrodes having sidewalls covered by insulating sidewall spacers and an upper surface covered by an insulating cap, comprising the steps of: forming a passivation layer on the exposed surface of the substrate; etching through selected portions of the passivation layer to expose the insulating cap of selected ones of the plurality of gate electrodes and to expose regions of the substrate adjacent to each of the plurality of gate electrodes; selectively forming a first conductor on said exposed regions of the substrate and the insulating cap on the adjacent gate electrode; treating the substrate in an etchant that removes the exposed insulator caps without appreciably etching said first conductor, to expose said selected ones of the plurality of gate electrodes; and forming a second conductor on said selected ones of the plurality of gate electrodes.
Claim 12
Dependent Claim
163 words
A process for forming borderless contacts on a semiconductor substrate having a plurality of gate electrodes disposed on an exposed surface thereof, each of the plurality of gate electrodes having sidewalls covered by insulating sidewall spacers and an upper surface covered by an insulating cap, comprising the steps of: forming a passivation layer on the exposed surface of the substrate; etching through selected portions of the passivation layer to expose the insulating cap of selected ones of the plurality of gate electrodes and to expose regions of the substrate adjacent to each of the plurality of gate electrodes; selectively forming a first conductor on said exposed regions of the substrate and the insulating cap on the adjacent gate electrode; treating the substrate in an etchant that removes the exposed insulator caps without appreciably etching said first conductor, to expose said selected ones of the plurality of gate electrodes; and forming a second conductor on said selected ones of the plurality of gate electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |