US4631806A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing integrated circuit structures
Assignee: Verizon Laboratories Inc
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Filing: 1985-05-22
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Granted: 1986-12-30
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Expires: 2005-05-22
Abstract
Abstract Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.
Inventors
- 👤 Paul E. Poppert
- 👤 Marvin J. Tabasky
- 👤 Eugene O. Degenkolb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:57
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/202; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/10; Y10S148/106
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
228 words
The method of producing interconnections in an integrated circuit structure comprising providing an integrated circuit sturcture including a body of silicon and having a surface coated with a layer of an adherent nonconductive protective material of silicon dioxide, silicon nitride, or silicon dioxide and silicon nitride; depositing masking material on the layer of protective material including the steps of depositing a layer of a planarizing material on said layer of protective material, and depositing a layer of silicon on said layer of planarizing material; forming openings in said masking material and in said layer of protective material to expose contact areas on said surface of the integrated circuit structure; depositing a first conductive material overlying the remainder of the masking material and the contact areas exposed at the openings in the masking material and in the protective material; removing the remainder of the masking material and the first conductive material thereon leaving first conductive material on said contact areas; depositing a second conductive material overlying said protective material and the first conductive material on said contact areas; and selectively removing portions of said second conductive material to form conductive members overlying the first conductive material on said contact areas and overlying portions of said layer of protective material; wherein said first conductive material is a metal which provides a barrier to diffusion of the second conductive material therethrough.
Claim 2
Independent Claim
228 words
The method of producing interconnections in an integrated circuit structure comprising providing an integrated circuit sturcture including a body of silicon and having a surface coated with a layer of an adherent nonconductive protective material of silicon dioxide, silicon nitride, or silicon dioxide and silicon nitride; depositing masking material on the layer of protective material including the steps of depositing a layer of a planarizing material on said layer of protective material, and depositing a layer of silicon on said layer of planarizing material; forming openings in said masking material and in said layer of protective material to expose contact areas on said surface of the integrated circuit structure; depositing a first conductive material overlying the remainder of the masking material and the contact areas exposed at the openings in the masking material and in the protective material; removing the remainder of the masking material and the first conductive material thereon leaving first conductive material on said contact areas; depositing a second conductive material overlying said protective material and the first conductive material on said contact areas; and selectively removing portions of said second conductive material to form conductive members overlying the first conductive material on said contact areas and overlying portions of said layer of protective material; wherein said first conductive material is a metal which provides a barrier to diffusion of the second conductive material therethrough.
Claim 3
Dependent Claim
118 words
The method in accordance with claim 1 wherein forming openings in said masking material includes depositing a layer of a resist material on said layer of silicon, forming openings in the resist material to define the pattern of contact areas, etching to remove the silicon exposed by the openings in the resist material and to form openings in the layer of silicon, etching to remove the planarizing material exposed by the openings in the layer of silicon to form openings in the layer of planarizing material, and etching to remove the nonconductive protective material exposed by the openings in the layer of planarizing material and to expose said contact areas on the surface of the integrated circuit structure.
Claim 4
Dependent Claim
14 words
The method in accordance with claim 2 wherein said second conductive material is aluminum.
Claim 5
Dependent Claim
87 words
The method in accordance with claim 3 wherein selectively removing portions of said second conductive material includes depositing masking material on the second conductive material including the steps of depositing a layer of a planarizing material on the second conductive material, and depositing a layer of silicon on the layer of planarizing material; selectively removing portions of said masking material overlying said portions of said second conductive material to be removed; and etching to remove the exposed portions of said second conductive material leaving said conductive members.
Claim 6
Dependent Claim
40 words
The method in accordance with claim 4 wherein removing the remainder of the masking material and the first conductive material thereon includes agitating the integrated circuit structure while it is immersed in a solvent capable of dissolving the planarizing material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |