Process for forming metallic ground grid for integrated circuits

Claim 2

A process for fabricating an integrated circuit having a plurality of planar regions of a first conductivity type separated by planar isolation barriers of an opposed second conductivity type and having semiconductor components formed in said planar regions comprising: forming a first insulated layer on said planar regions with said planar isolation barriers exposed; forming a first continuous conductor on said exposed isolation barriers having a thickness less than the thickness of said first insulated layer; forming a second insulated layer on said first conductor having a thickness sufficient to produce a substantially planar surface with said first insulated layer; forming select apertures in said first and second insulated layers to expose planar areas of said semiconductor components and areas of said first conductor respectively; and forming a plurality of second conductors interconnecting said exposed planar areas and said exposed first conductor areas.

Claim 3

A process as in claim 1, wherein forming said first conductor and said second insulated layer includes applying said first conductor having a thickness less than the thickness of said first insulated layer and anodizing said first conductor to produce said first conductor and second insulated layer having a combined thickness sufficient to produce said substantially planar surface with said first insulated layer.

Claim 4

A process as in claim 1, wherein said second insulated layer is formed to have a thickness approximately equal to the thickness of said first insulated layer minus the thickness of said first conductor.

Claim 5

A process as in claim 1, wherein forming said first conductor and said second insulated layer includes applying said first conductor having a thickness substantially the thickness of said first insulated layer and anodizing said first conductor to produce said first conductor and second insulated layer having a combined thickness slightly greater than said first insulated layer and sufficient to produce said substantially planar surface with said first insulated layer.

Claim 6

A process as in claim 1, wherein: forming said first insulated layer includes forming an insulated layer on said planar regions of a first thickness and defining a second planar surface and forming openings in said first insulated layer using a masking material of a second thickness to expose said isolation barrier; and wherein forming said first conductor includes applying a layer of said first conductor of a third thickness, less than the sum of said first and second thicknesses on said masking material and said exposed isolation barriers and removing said masking material and said first conductor superimposed thereon.

Claim 7

A process as in claim 5, wherein forming second insulated layer includes oxidizing said first conductor sufficiently to produce a surface substantially planar with said second planar surface.

Claim 8

A process as in claim 1, wherein forming said plurality of second conductors includes applying a layer of conductive material and delineating said layer of conductive material to interconnect said exposed planar areas of said semiconductor components and areas of said first conductor.

Claim 9

A process as in claim 1, wherein forming said first conductor and said second insulated layer includes applying said first conductor having a thickness substantially the thickness of said first insulated layer, increasing the thickness of said first insulated layer, and anodizing said first conductor to produce said first conductor and second insulated layer having a combined thickness sufficient to produce said substantially planar surface with said first insulated layer of increased thickness.

Claim 10

A process for fabricating an integrated circuit having a plurality of planar regions of a first conductivity type separated by planar isolation barriers of an opposed second conductivity type and having semiconductor components formed in said planar regions comprising: forming a first insulated layer on said planar regions with said planar isolation barriers exposed; forming a first continuous conductor on said exposed isolation barriers having a thickness less than the thickness of said first insulated layer; oxidizing said first conductor to form a second insulated layer on said first conductor having a thickness sufficient to produce a substantially planar surface with said first insulated layer; forming select apertures in said first and second insulated layers to expose planar areas of said semiconductor components and areas of said first conductor respectively; and forming a plurality of second conductors interconnecting said exposed planar areas and said exposed first conductor areas.

Claim 11

A process for fabricating an integrated circuit having a plurality of planar regions of a first conductivity type separated by planar isolation barriers of an opposed second conductivity type and having semiconductor components formed in said planar regions comprising: forming a first insulated layer on said planar regions with said planar isolation barriers exposed; forming a first continuous conductor on said exposed isolation barriers having a thickness less than the thickness of said first insulated layer; oxidizing said first conductor to form a second insulated layer on said first conductor having a thickness sufficient to produce a substantially planar surface with said first insulated layer; forming select apertures in said first and second insulated layers to expose planar areas of said semiconductor components and areas of said first conductor respectively; and forming a plurality of second conductors interconnecting said exposed planar areas and said exposed first conductor areas.