US6763485B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Position independent testing of circuits
Assignee: Texas Instruments Inc
•
Filing: 2002-04-02
•
Granted: 2004-07-13
•
Expires: 2022-04-02
Abstract
Abstract Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:01
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318558; G01R31/318572
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
A process of testing an integrated circuit comprising: A. configuring a functional circuit into a test mode; B. capturing one response data bit output from each of plural scan paths, associated with the functional circuit, into a scan collector; C. simultaneously loading stimulus data bits into a scan distributor and unloading response data bits from the scan collector; D. shifting the scan paths one bit to load each scan path with one stimulus data bit from the scan distributor; E. if the scan paths are not filled with stimulus data bits, then repeating steps B, C, and D; F. if the scan paths are full of stimulus data bits, then applying the stimulus data bits in the scan paths to the functional circuit, capturing response data bits from the functional circuit in the scan paths, and returning to step B.
Claim 2
Dependent Claim
140 words
A process of testing an integrated circuit comprising: A. configuring a functional circuit into a test mode; B. capturing one response data bit output from each of plural scan paths, associated with the functional circuit, into a scan collector; C. simultaneously loading stimulus data bits into a scan distributor and unloading response data bits from the scan collector; D. shifting the scan paths one bit to load each scan path with one stimulus data bit from the scan distributor; E. if the scan paths are not filled with stimulus data bits, then repeating steps B, C, and D; F. if the scan paths are full of stimulus data bits, then applying the stimulus data bits in the scan paths to the functional circuit, capturing response data bits from the functional circuit in the scan paths, and returning to step B.
Claim 3
Dependent Claim
31 words
The process of claim 1 including, if the scan paths are full of stimulus data bits and the test is to end, then configuring the functional circuit into a normal mode.
Claim 4
Dependent Claim
29 words
The process of claim 1 in which the capturing includes capturing one response data bit output from each of plural scan paths in parallel into a parallel scan collector.
Claim 5
Dependent Claim
20 words
The process of claim 1 in which the loading includes serially loading stimulus data bits into a parallel scan distributor.
Claim 6
Dependent Claim
20 words
The process of claim 1 in which the unloading includes serially unloading response data bits from a parallel scan collector.
Claim 7
Dependent Claim
25 words
The process of claim 1 in which the loading includes serially loading stimulus data bits into a parallel scan distributor from a single bond pad.
Claim 8
Dependent Claim
25 words
The process of claim 1 in which the unloading includes serially unloading response data bits from a parallel scan collector to a single bond pad.
Claim 9
Dependent Claim
32 words
The process of claim 1 in which the shifting includes serially shifting the scan paths one bit to load each scan path with one stimulus data bit from the parallel scan distributor.
References Cited (Backward Citations)
US3657527A
Cited
US3633100A
Cited
US3651315A
Cited
US3824678A
Cited
US3838264A
Cited
US3739193A
Cited
US3723868A
Cited
US3789359A
Cited
US3831149A
Cited
US3826909A
Cited
US3873818A
Cited
US3976940A
Cited
US4023142A
Cited
US4086375A
Cited
US4092733A
Cited
US4066882A
Cited
USRE31056E
Cited
US4108359A
Cited
US4161276A
Cited
US4146835A
Cited
US4286173A
Cited
US4216539A
Cited
US4242751A
Cited
US4309767A
Cited
US4268902A
Cited
US4339710A
Cited
US4264807A
Cited
US4308616A
Cited
US4553090A
Cited
US4312066A
Cited
US4366478A
Cited
US4365334A
Cited
US4390969A
Cited
US4426697A
Cited
US4484329A
Cited
US4357703A
Cited
JPS5794857A
Cited
US4439858A
Cited
US4494066A
Cited
US4441075A
Cited
US4504784A
Cited
US4433413A
Cited
US4483002A
Cited
JPS58191021A
Cited
US4498172A
Cited
US4514845A
Cited
US4493077A
Cited
US4503536A
Cited
US4597042A
Cited
US4519078A
Cited
US4488259A
Cited
US4513418A
Cited
US4513373A
Cited
US4642561B1
Cited
US4642561A
Cited
US4575674A
Cited
US4587609A
Cited
US4646299A
Cited
US4627018A
Cited
EP0136174B1
Cited
US4618956A
Cited
US4612499A
Cited
US4594711A
Cited
US4597080A
Cited
US4577318A
Cited
US4534028A
Cited
US4621363A
Cited
US4680733A
Cited
JPS60140834A
Cited
EP0148403B1
Cited
US4680539A
Cited
US4896262A
Cited
US4601034A
Cited
US4878168A
Cited
US4646298A
Cited
US4598401A
Cited
US4651088A
Cited
US4635193A
Cited
US4800418A
Cited
US4628511A
Cited
US4694293A
Cited
US4638313A
Cited
US4615029A
Cited
US4669061A
Cited
EP0195164B1
Cited
US4764926A
Cited
US4602210A
Cited
EP0190494B1
Cited
US4740970A
Cited
US4679192A
Cited
US4855954A
Cited
US4701916A
Cited
US4752929A
Cited
US4674089A
Cited
US4743841A
Cited
US4745355A
Cited
US4801870A
Cited
US4687988A
Cited
US4635261A
Cited
US4961053A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-07-13 | 2008-01-12 | 2008-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-07-13 | 2012-01-12 | 2012-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-07-13 | 2016-01-12 | 2016-07-13 | $7700.00 | Window Closed / Lapsed |