EP0148403B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Linear feedback shift register
Assignee: International Business Machines Corp
•
Filing: 1984-12-04
•
Granted: 1991-02-20
•
Expires: 2004-12-04
Abstract
Abstract A linear feedback shift register for inclusion in a VLSI circuit. During a test function for the VLSI circuit, the shift register can be programmed into an LSSD test mode, or two generate test patterns for the VLSI circuit, and to perform a corresponding signature analysis on hashing functions on the VLSI response to the test pattern. The linear feedback shift register can be programmed on the VLSI chip to perform any of these test functions. During normal VLSI circuit operation, the shift register is transparent to logic signals carried by the VLSI circuit.
Inventors
- 👤 Mon Yen Tsai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G11; G11C; G11C19/00; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
275 words
A programmable linear feedback shift register (13, 14) for self-testing a VLSI circuit, the shift register having a plurality of one bit stages (S0-S4), each stage comprising: a one bit register (23) for storing and transmitting a data bit during a normal VLSI circuit operation and for storing and transmitting a test bit during a test operation, a shift in line (SHIFT IN) connected to a shift out line (SHIFT OUT) of a preceeding stage, a feedback input line (FBI) connectable to the shift out line of a succeeding stage and a number of control signal gates (TEST1, TEST2, NORM IN, FD, IN), whereby data bits can be read in and out of the shift register during normal VLSI operation and test bits can be read in, shifted and read out of the shift register during test operation, characterized in that each stage comprises further: a first exclusive NOR circuit (20) having a first input (22) connectable to an input signal line (INPUT) from the circuit under test, a second input (A) connected to the output of a second exclusive NOR circuit (19), and an output connected over a first test gate (27) to the one bit register (23), said second exclusive NOR circuit (19) having as a first input said shift in line (SHIFT IN) and as a second input said feedback input line (FBI) of the stage, and a second test gate (28) connecting the output of the one bit register to the shift out line of the stage, said first and second test gates (27, 28) being controlled by first and second test clock signals (TEST1, TEST2) respectively during a test operation.
Claim 2
Dependent Claim
30 words
A shift register according to claim 1, wherein said control signal gates comprises gates (FD,26;IN,22) for selecting various test mode operations such as pattern generator mode or signature analyzer mode.
Claim 3
Dependent Claim
28 words
A shift register according to claim 1, wherein the second test gate (28) is connected over an inverter circuit (30) to the shift out line of the stage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.