EP0190494B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit arrangement for use in an integrated circuit having built in self-test design
Assignee: Roke Manor Research Ltd
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Filing: 1985-12-05
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Granted: 1990-09-19
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Expires: 2005-12-05
Abstract
Abstract A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates (8, 3) coupled to a flip-flop (2) via a third gate (4). The present invention provides a multiplexer (M) coupled to one input of the first gate (8), the multiplexer (M) being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate (8) and a fourth gate (13) coupled to an input of the second gate (3), the fourth gate (13) having an input connected to receive a signal dependent on the control signal to the data selector means (M).
Inventors
- 👤 David Frank Burrows
- 👤 Mark Paraskeva
- 👤 William Lawrence Knight
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 14:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/318541; G01R31/318572
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
201 words
A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates (8, 3), each of which has a first input coupled to a respective control line, a third gate (4) providing an exclusive-OR or an exclusive-NOR function and having a first input coupled to receive the output of the first gate and a second input coupled to receive the output of the second gate, and a flip-flop (2) coupled to receive the output of the third gate (4), characterised by data selector means (M) coupled to a second input of the first gate (8), the data selector means (M) being controllable by a control signal to feed either input data derived external to the circuit arrangement or output data from said flip-flop forming the output element of the circuit arrangement to the second input of the first gate (8) and a fourth gate (13) having an output coupled to a second input of the second gate (3), the fourth gate (13) having a first input connected to receive a signal dependent on the control signal to the data selector means (M) and a second input for receiving input signals.
Claim 2
Dependent Claim
201 words
A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates (8, 3), each of which has a first input coupled to a respective control line, a third gate (4) providing an exclusive-OR or an exclusive-NOR function and having a first input coupled to receive the output of the first gate and a second input coupled to receive the output of the second gate, and a flip-flop (2) coupled to receive the output of the third gate (4), characterised by data selector means (M) coupled to a second input of the first gate (8), the data selector means (M) being controllable by a control signal to feed either input data derived external to the circuit arrangement or output data from said flip-flop forming the output element of the circuit arrangement to the second input of the first gate (8) and a fourth gate (13) having an output coupled to a second input of the second gate (3), the fourth gate (13) having a first input connected to receive a signal dependent on the control signal to the data selector means (M) and a second input for receiving input signals.
Claim 3
Dependent Claim
30 words
A circuit arrangement as claimed in claim 1, wherein the first, second and fourth gates (8, 3, 13) are NAND gates and the third gate (4) is an Exclusive-NOR gate.
Claim 4
Dependent Claim
36 words
A circuit arrangement as claimed in claim 1, wherein the first and second gates (8, 3) are AND gates, the third gate (4) is an Exclusive-OR gate and the fourth gate (13) is an OR gate.
Claim 5
Dependent Claim
27 words
A register element comprising a plurality of circuit arrangements as claimed in any one of claims 1 to 3, the circuit arrangements being coupled together in series.
Claim 6
Dependent Claim
49 words
A register element as claimed in claim 4 wherein the outputs of two or more of the flip-flops in the series are coupled to the inputs of an Exclusive-NOR gate the output of which is coupled to the input of one or more of the flip-flops in the series.
Claim 7
Dependent Claim
81 words
A register element comprising a plurality of circuit arrangements as claimed in claim 1, the circuit arrangements being coupled together in series wherein the third gate (4) in at least one of the circuit arrangements is an Exclusive-NOR gate and the outputs of two or more of the flip-flops in the series are coupled to the inputs of another Exclusive-NOR gate the output of which is coupled to the input of the one or more of the flip-flops in the series.
Claim 8
Dependent Claim
35 words
A register element as claimed in claim 6, wherein the output of said another Exclusive-NOR gate is coupled to the input of the first flip-flop via a multiplexer, an AND gate and an Exclusive-NOR gate.
Claim 9
Dependent Claim
76 words
An integrated circuit having a built-in self test design, the integrated circuit including a plurality of the register elements as claimed in any one of claims 4 to 7, the register elements being coupled to combinatorial logic circuits, control means being provided for selectively controlling the functional modes of each register element and for selectively controlling predefined groups of register elements to operate in different functional modes to effect test operations to the combinatorial logic circuits.
References Cited (Backward Citations)
No citation records indexed.
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