US4618956A
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Method of operating enhanced alu test hardware
Assignee: Hewlett Packard Development Co LP
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Filing: 1983-09-29
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Granted: 1986-10-21
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Expires: 2003-09-29
Abstract
Abstract Method and hardware associated with an arithmetic logic unit (ALU) in a central processing unit of a data processor provides for testing the inputs to the ALU to see if logical AND is zero or the two inputs are equal while allowing the ALU to perform another function at the time these tests are made.
Inventors
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30021; G06F11/00; G06F11/22; G06F11/2205; G06F11/2226; G06F9/30094
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
189 words
A method of operating a loop counter routine in a central processing unit of a digital computer, including the steps of: (a) providing a data input, representative of a first desired quantity, to a first input of an arithmetic logic unit, (b) providing a data input representing a second desired quantity to a second input of said arithmetic logic unit, (c) performing a subtract operation using said arithmetic logic unit during a first clock period, (d) performing an equivalence test on said first and second arithmetic logic unit inputs external to said arithmetic logic unit during said first clock period, (e) terminating said loop counter routine if the result of said equivalence test indicates that first and second arithmetic logic unit inputs are equal and returning the results of said arithmetic logic unit subtract operation to said first input of said arithmetic logic unit if the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are not equal, (f) Repeating steps (b) through (e) until the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are equal.
Claim 2
Independent Claim
189 words
A method of operating a loop counter routine in a central processing unit of a digital computer, including the steps of: (a) providing a data input, representative of a first desired quantity, to a first input of an arithmetic logic unit, (b) providing a data input representing a second desired quantity to a second input of said arithmetic logic unit, (c) performing a subtract operation using said arithmetic logic unit during a first clock period, (d) performing an equivalence test on said first and second arithmetic logic unit inputs external to said arithmetic logic unit during said first clock period, (e) terminating said loop counter routine if the result of said equivalence test indicates that first and second arithmetic logic unit inputs are equal and returning the results of said arithmetic logic unit subtract operation to said first input of said arithmetic logic unit if the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are not equal, (f) Repeating steps (b) through (e) until the result of said equivalence test indicates that said first and second arithmetic logic unit inputs are equal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |