US4680539A
Expired / Lapsed
US
⏱️ 0.0 years remaining
General linear shift register
Assignee: International Business Machines Corp
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Filing: 1983-12-30
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Granted: 1987-07-14
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Expires: 2003-12-30
Abstract
Abstract A linear feedback shift register for inclusion in a VLSI circuit. During a test function for the VLSI circuit, the shift register can be programmed into an LSSD test mode, or two generate test patterns for the VLSI circuit, and to perform a corresponding signature analysis on hashing functions on the VLSI response to the test pattern. The linear feedback shift register can be programmed on the VLSI chip to perform any of these test functions. During normal VLSI circuit operation, the shift register is transparent to logic signals carried by the VLSI circuit.
Inventors
- 👤 Mon Y. Tsai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G11; G11C; G11C19/00; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
157 words
A programmable linear feedback shift register for self-testing a VLSI circuit, said register having a plurality of two bit stages, each stage comprising: a first exclusive NOR circuit for receiving a binary shift signal from a preceding stage, and a feedback signal; a second exclusive NOR circuit for receiving a first logical signal from said first exclusive NOR circuit, and an input signal; a cross-coupled register connected to receive a signal from said VLSI circuit during normal VLSI circuit operation, and a signal from said second exclusive NOR circuit during a test operation; an inverter circuit for receiving an output signal from said cross-coupled register, said inverter circuit supplying a shift signal for application to a subsequent stage first exclusive NOR circuit; and means for coupling said second exclusive NOR circuit output during a first test interval to said cross-coupled register, and an output signal from said cross-coupled register to said inverter during a second test interval.
Claim 2
Dependent Claim
157 words
A programmable linear feedback shift register for self-testing a VLSI circuit, said register having a plurality of two bit stages, each stage comprising: a first exclusive NOR circuit for receiving a binary shift signal from a preceding stage, and a feedback signal; a second exclusive NOR circuit for receiving a first logical signal from said first exclusive NOR circuit, and an input signal; a cross-coupled register connected to receive a signal from said VLSI circuit during normal VLSI circuit operation, and a signal from said second exclusive NOR circuit during a test operation; an inverter circuit for receiving an output signal from said cross-coupled register, said inverter circuit supplying a shift signal for application to a subsequent stage first exclusive NOR circuit; and means for coupling said second exclusive NOR circuit output during a first test interval to said cross-coupled register, and an output signal from said cross-coupled register to said inverter during a second test interval.
Claim 3
Dependent Claim
67 words
The programmable linear feedback shift register of claim 1 wherein said first exclusive NOR circuit comprises: a pair of cross-coupled FETs having one input connected to receive a shift signal, and a remaining input; and a feedback gate for applying a binary feedback signal to said remaining input and applying a logical zero binary state signal to said remaining input in the absence of a feedback pulse.
Claim 4
Dependent Claim
34 words
The programmable linear feedback shift register of claim 2 wherein said second exclusive NOR circuit is coupled through a gate circuit means to receive an input signal in response to an enabling INPUT signal.
Claim 5
Dependent Claim
75 words
The programmable linear feedback shift register of claim 1 wherein said cross-coupled register comprises: first and second series transistor pairs each transistor of each pair being of an opposite conductivity type, one of said transistors of a pair having a gate connected to the series connection point of the remaining pair of transistors; and a transistor coupling the series connection point of said remaining pair to the gate of a transistor of said one pair.
Claim 6
Dependent Claim
140 words
In a VLSI circuit, a register for performing testing functions for a remaining portion of said VLSI circuit comprising: a multicell register, each of said cells comprising: a one bit register; a first exclusive NOR gate; a second exclusive NOR gate; said first exclusive NOR gate having a first input connected to receive the output signal from said second exclusive NOR gate, and a second input adapted to receive a logical INPUT signal; said second exclusive NOR gate having first and second inputs adapted to receive a SHIFT IN signal and FEEDBACK signal; and means for connecting the output of said first exclusive NOR gate to said one bit register input and the output of said one bit register to an input of the second exclusive NOR gate of another of said cells during respective first and second test intervals.
Claim 7
Dependent Claim
140 words
In a VLSI circuit, a register for performing testing functions for a remaining portion of said VLSI circuit comprising: a multicell register, each of said cells comprising: a one bit register; a first exclusive NOR gate; a second exclusive NOR gate; said first exclusive NOR gate having a first input connected to receive the output signal from said second exclusive NOR gate, and a second input adapted to receive a logical INPUT signal; said second exclusive NOR gate having first and second inputs adapted to receive a SHIFT IN signal and FEEDBACK signal; and means for connecting the output of said first exclusive NOR gate to said one bit register input and the output of said one bit register to an input of the second exclusive NOR gate of another of said cells during respective first and second test intervals.
Claim 8
Dependent Claim
23 words
The register of claim 5 further comprising a gate circuit connected to control a signal entering said first exclusive NOR gate second input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |