← Back to Patent Explorer
US4309767A Expired / Lapsed US ⏱️ 0.0 years remaining

Monitor system for a digital signal

Assignee: Toshiba Corp
•
Filing: 1979-08-21
•
Granted: 1982-01-05
•
Expires: 1999-08-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A monitor system comprising: an adder for summing up a plurality of unknown analog electric quantity signals denoting the operating conditions of such as a transmission line; a multiplexer for generating output signals corresponding to the plural analog electric quantity signals and also to a signal denoting the result of addition made by said adder; an A-D converter for converting output analog signals from the multiplexer into digital signals; and a monitor which sums up those of the output digital signals from the A-D converter which correspond to said plural analog electric quantity signals, compares a signal denoting the result of said addition with a digital signal converted from an output signal from the adder, receives an error detection signal denoting the known prescribed electric quantity converted into a digital signal through the multiplexer and A-D converter, and judges the operating condition of the A-D converter from the contents of said received digital signal.

Inventors

  • 👤 Fumio Andow
  • 👤 Kyotaro Kondow
  • 👤 Eiichi Okamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 06:40
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1071; H03M1/12; H03M1/1205

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 210 words
A monitor system connected to a digital data processing system, which comprises: an analog arithmetic operation device for arithmetically processing a plurality of unknown analog electric quantity signals; a multiplexer which is supplied with an output signal from said arithmetic operation device, said plural analog electric quantity signals and an error detection signal denoting a known prescribed electric quantity, and generates output signals corresponding to the plural analog electric quantity signals, the output signal from said arithmetic operation device and the error detection signal successively in a certain prescribed order; an analog-digital converter for converting output analog signals from the multiplexer into digital signals and for delivering the digital signals to said digital data processing system; and a monitor connected to receive the output of the A-D converter and including a digital arithmetic operation device for performing an arithmetic processing corresponding to that of the analog arithmetic operation device, a first comparator for comparing the output of the digital arithmetic operation device and an A-D converted output signal of said analog arithmetic operation device, a discrete register for storing a digital signal of a prescribed digital value, and a second comparator for comparing a digital error detection signal obtained through the A-D converter and the output of the discrete register.
Claim 2
Dependent Claim 210 words
A monitor system connected to a digital data processing system, which comprises: an analog arithmetic operation device for arithmetically processing a plurality of unknown analog electric quantity signals; a multiplexer which is supplied with an output signal from said arithmetic operation device, said plural analog electric quantity signals and an error detection signal denoting a known prescribed electric quantity, and generates output signals corresponding to the plural analog electric quantity signals, the output signal from said arithmetic operation device and the error detection signal successively in a certain prescribed order; an analog-digital converter for converting output analog signals from the multiplexer into digital signals and for delivering the digital signals to said digital data processing system; and a monitor connected to receive the output of the A-D converter and including a digital arithmetic operation device for performing an arithmetic processing corresponding to that of the analog arithmetic operation device, a first comparator for comparing the output of the digital arithmetic operation device and an A-D converted output signal of said analog arithmetic operation device, a discrete register for storing a digital signal of a prescribed digital value, and a second comparator for comparing a digital error detection signal obtained through the A-D converter and the output of the discrete register.
Claim 3
Dependent Claim 38 words
The monitor system according to claim 1, which further comprises means for selectively supplying the error detection signal denoting the known prescribed electric quantity and output electric quantity signals from the analog arithmetic operation device to the multiplexer.
Claim 4
Dependent Claim 43 words
The monitor system according to claim 1, which further comprises means for selectively supplying the error detection signal denoting the known prescribed electric quantity and the plurality of unknown analog electric quantity signals to the input terminals of the analog arithmetic operation device.
Claim 5
Dependent Claim 33 words
The monitor system according to claim 1, further comprising a preprocessing device having an input connected to said unknown analog electric quantity signals and an output connected to the input of said multiplexer.
Claim 6
Dependent Claim 22 words
The monitor system according to claim 4, wherein the preprocessing device comprises at least one of a filter and a sample-hold circuit.
Claim 7
Dependent Claim 62 words
The monitor system according to claim 1 wherein: said discrete register stores a digital signal corresponding to said error detection signal; said monitor further comprises a second discrete register for storing a digital output signal from said A-D converter obtained by converting said error detection signal; and said second comparator compares the output of said discrete register and said second discrete register.
Claim 8
Dependent Claim 16 words
The monitor system according to claim 1, wherein said analog arithmetic operation device includes a subtracter.

References Cited (Backward Citations)

US3623155A Cited
US3653037A Cited
US3745561A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-01-04 1985-07-06 1986-01-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-01-04 1989-07-06 1990-01-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-01-04 1993-07-06 1994-01-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag