Testing of nonlinear circuits by comparison with a reference simulation with means to eliminate errors caused by critical race conditions

Claim 2

Apparatus for testing nonlinear circuits having n-level logic comprising: means for generating an n-level electrical signal test pattern, each level being equivalent to one of said logic levels; means for applying said test pattern to at least one input in the circuit being tested; means for converting said test pattern to an (n+ 1)-level signal pattern in which n levels represent the n levels in the circuit logic and one level represents an indeterminate level in said circuit logic; a reference simulation of the circuit being tested adapted to receive said (n+ 1) signal pattern at at least one input corresponding to said at least one input in the circuit being tested and to provide a resulting (n+ 1)-level output; means for applying said (n+ 1) signal pattern to said reference simulation; means for sensing the one level in the simulation output representing an indeterminate level in said circuit logic; means for converting the simulation output back to an n-level Signal pattern; means for comparing the n-level output from the circuit being tested with the corresponding n-level converted output from the reference simulation; means for applying said output from the circuit being tested to said comparing means; and means for applying said corresponding converted reference simulation output to said comparing means.

Claim 3

The apparatus of claim 1, further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of said reference simulation output sensed at the one level representing an indeterminate level in said circuit logic.

Claim 4

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying the three-level signal pattern to said reference simulation at said inputs; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 5

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying the three-level signal pattern to said reference simulation at said inputs; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 6

The apparatus of claim 3, further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of the reference simulation output sensed at the third level.

Claim 7

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 8

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 9

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said cIrcuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for converting said first and second levels in said three-level output back to the equivalent levels in said bilevel signal pattern and for applying the converted pattern to said comparing means; and means for inhibiting a comparison by said comparing means of that portion of said three-level output remaining at the third level.

Claim 10

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said cIrcuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level pattern which has first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate binary circuit state; a reference simulation of said circuit adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for converting said first and second levels in said three-level output back to the equivalent levels in said bilevel signal pattern and for applying the converted pattern to said comparing means; and means for inhibiting a comparison by said comparing means of that portion of said three-level output remaining at the third level.

Claim 11

The apparatus of claim 1 wherein: said means for converting the test pattern converts said pattern into an (n+ 1)-level signal pattern formed in double-rail binary logic; and said reference simulation of the circuit being tested is formed in double-rail binary logic.

Claim 12

The apparatus of claim 7, further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of said reference simulation output sensed at the one level representing an indeterminate level in said circuit logic.

Claim 13

The apparatus of claim 3 wherein: said means for converting the bilevel signal pattern converts said pattern to a three-level signal pattern formed in double-rail binary logic; and said reference simulation of the circuit is formed in double-rail binary logic.

Claim 14

The apparatus of claim 9, further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of the reference simulation output sensed at the third level.

Claim 15

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level signal pattern formed in double-rail binary logic, said three-level signal pattern having first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate circuit state; a reference simulation of said circuit formed in double-rail binary logic adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 16

In apparatus for testing nonlinear binary circuits comprising means for applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal pattern to a three-level signal pattern formed in double-rail binary logic, said three-level signal pattern having first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate circuit state; a reference simulation of said circuit formed in double-rail binary logic adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 17

The apparatus of claim 11, further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of the reference simulation output sensed at the third level.

Claim 18

In apparatus for testing nonlinear binary circuits comprising means for applying A bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal to a three-level signal pattern formed in four-level double-rail binary logic, said three-level signal pattern having first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate circuit state, the fourth level in said double-rail logic being representative of an error condition; a reference simulation of said circuit formed in double-rail binary logic adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; means for sensing said fourth level in the simulation output indicative of an error condition; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 19

In apparatus for testing nonlinear binary circuits comprising means for applying A bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of the binary circuit states and means for applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and means for comparing corresponding resulting outputs from said circuit and said reference simulation, the improvement comprising: means for converting the bilevel signal to a three-level signal pattern formed in four-level double-rail binary logic, said three-level signal pattern having first and second levels representative of the two levels in the bilevel signal pattern and a third level representative of an indeterminate circuit state, the fourth level in said double-rail logic being representative of an error condition; a reference simulation of said circuit formed in double-rail binary logic adapted to receive said three-level signal pattern at inputs corresponding to the input points in the circuit being tested and to provide a resulting three-level output; means for applying said three-level signal pattern to said reference simulation including means permitting the application of a third level signal during a change between said first and second level signals being applied to a simulation input; means for sensing said third level in the simulation output; means for sensing said fourth level in the simulation output indicative of an error condition; and means for converting the simulation output back to a bilevel signal pattern and for applying said converted pattern to said comparing means.

Claim 20

The apparatus of claim 1 wherein said means for generating a test pattern generate a random test pattern.

Claim 21

The apparatus of claim 3 wherein said bilevel electrical signal pattern is a random pattern.

Claim 22

The apparatus of claim 4 wherein said bilevel electrical signal pattern is a random pattern.

Claim 23

The apparatus of claim 6 wherein said bilevel electrical signal pattern is a random pattern.

Claim 24

The apparatus of claim 7 wherein said bilevel electrical signal pattern is a random pattern.

Claim 25

The apparatus of claim 18 further including means responsive to said sensing means for inhibiting a comparison by said comparing means of that portion of said reference simulation output sensed at the one level representing an indeterminate level in said circuit logic.

Claim 26

The apparatus of claim 9 wherein said bilevel electrical signal pattern is a random pattern.

Claim 27

The apparatus of claim 12 wherein said bilevel electrical signal pattern is a random pattern.

Claim 28

In a method for testing nonlinear circuits having n-level logic comprising applying an n-level electrical signal pattern to at least one input in the circuit being tested, each level being equivalent to one of said logic levels and applying said signal pattern to at least one corresponding input in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of determining whether a changing n-level signal pattern produces race conditions in sequential circuits being tested critical to at least a portion of the resulting outputs by a method comprising: converting the n-level signal pattern to an (n+ 1)-level signal pattern, in which n levels represent the n levels in the circuit logic and one level represents an indeterminate level in said circuit logic; applying said (n+ 1) signal pattern to a reference simulation of said circuit adapted to receive said (n+ 1) signal pattern at at least one input corresponding to said at least one input in the circuit being tested and to provide a resulting (n+ 1) level output, the sequence of application of said (n+ 1) signal pattern to said reference simulation being such that when a given said simulation input is being changed from a first tO a second of said n logic levels, said one level representing the indeterminate logic level is applied to said given input before the second logic level; and determining whether said indeterminate logic level exists in at least a portion of said resulting simulation output after said change is completed, the existence of said indeterminate level indicating that the change produced race conditions critical to that portion of the output at the indeterminate level.

Claim 29

In a method for testing nonlinear circuits having n-level logic comprising applying an n-level electrical signal pattern to at least one input in the circuit being tested, each level being equivalent to one of said logic levels and applying said signal pattern to at least one corresponding input in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of determining whether a changing n-level signal pattern produces race conditions in sequential circuits being tested critical to at least a portion of the resulting outputs by a method comprising: converting the n-level signal pattern to an (n+ 1)-level signal pattern, in which n levels represent the n levels in the circuit logic and one level represents an indeterminate level in said circuit logic; applying said (n+ 1) signal pattern to a reference simulation of said circuit adapted to receive said (n+ 1) signal pattern at at least one input corresponding to said at least one input in the circuit being tested and to provide a resulting (n+ 1) level output, the sequence of application of said (n+ 1) signal pattern to said reference simulation being such that when a given said simulation input is being changed from a first tO a second of said n logic levels, said one level representing the indeterminate logic level is applied to said given input before the second logic level; and determining whether said indeterminate logic level exists in at least a portion of said resulting simulation output after said change is completed, the existence of said indeterminate level indicating that the change produced race conditions critical to that portion of the output at the indeterminate level.

Claim 30

The method of claim 22 including the further steps of: converting the simulation output back to an n-level signal pattern; and inhibiting the comparison of that portion of the simulation output remaining at the indeterminate level with the output of the circuit being tested.

Claim 31

In a method for testing nonlinear binary circuits comprising applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of said binary circuit states, and applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of determining whether a changing bilevel signal pattern produces race conditions in sequential circuits being tested critical to at least a portion of the resulting outputs by a method comprising: converting the bilevel signal pattern to a three-level signal pattern, in which the first and second levels represent the two levels in the circuit logic and the third level represents an indeterminate binary circuit state; applying said three-level signal pattern to a reference simulation of said circuit adapted to receive said three-level signal pattern at a plurality of inputs corresponding to said plurality of inputs in the circuit being tested and to provide a resulting three-level output, the sequence of application of said three-level signal pattern to said reference simulation being such that when a given one of said plurality of inputs is being changed from one of said first and second logic levels to the other, said third level is applied to said input being changed before the other changed level is applied; and determining whether said third logic level exists in at least a portion of said resulting simulation output after said change is completed, the existence of said third level indicating the change produced race conditions critical to that portion of the output at the third level.

Claim 32

In a method for testing nonlinear binary circuits comprising applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of said binary circuit states, and applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of determining whether a changing bilevel signal pattern produces race conditions in sequential circuits being tested critical to at least a portion of the resulting outputs by a method comprising: converting the bilevel signal pattern to a three-level signal pattern, in which the first and second levels represent the two levels in the circuit logic and the third level represents an indeterminate binary circuit state; applying said three-level signal pattern to a reference simulation of said circuit adapted to receive said three-level signal pattern at a plurality of inputs corresponding to said plurality of inputs in the circuit being tested and to provide a resulting three-level output, the sequence of application of said three-level signal pattern to said reference simulation being such that when a given one of said plurality of inputs is being changed from one of said first and second logic levels to the other, said third level is applied to said input being changed before the other changed level is applied; and determining whether said third logic level exists in at least a portion of said resulting simulation output after said change is completed, the existence of said third level indicating the change produced race conditions critical to that portion of the output at the third level.

Claim 33

The method of claim 24 including the further steps of converting the simulation output back to the bilevel signal pattern; and inhibiting the comparison of that portion of the simulation output remaining at the third level with the output of the circuit being tested.

Claim 34

The method of claim 24 wherein the three-level signal pattern is formed in double-rail logic.

Claim 35

The method of claim 25 wherein the three-level signal pattern is formed in double-rail logic.

Claim 36

The method of claim 22 wherein said applied n-level electrical signal pattern is randomly generated.

Claim 37

The method of claim 23 wherein said applied n-level electrical signal pattern is randomly generated.

Claim 38

The method of claim 24 wherein said applied bilevel electrical signal pattern is randomly generated.

Claim 39

The method of claim 25 wherein said applied bilevel electrical signal pattern is randomly generated.

Claim 40

The method of claim 26 wherein said applied bilevel electrical signal pattern is randomly generated.

Claim 41

The method of claim 27 wherein said applied bilevel electrical signal pattern is randomly generated.

Claim 42

In a method for testing nonlinear circuits having n-level logic comprising applying a changing n-level electrical signal pattern to a plurality of inputs in the circuit being tested, each level being equivalent to one of said logic levels, and synchronously applying said signal pattern respecTively to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of synchronizing the pattern applied to the circuit with the pattern applied to simulation and synchronizing the logic levels in said circuit with the logic levels in said simulation by a method comprising: applying to said plurality of inputs in the circuit being tested, an n-level signal synchronization pattern made up of an initial pattern increment comprising a plurality of signals, each of which is respectively applied to one of said plurality of inputs followed by a next subsequent pattern increment in which each of the signals is at a changed logic level from the coincident signal in the initial pattern; converting the n-level synchronization pattern to an (n+ 1)-level synchronization pattern, in which n levels represent the n levels in the circuit logic and one level represents an indeterminate level in said circuit logic; and applying said (n+ 1) synchronization pattern to a reference simulation of said circuit adapted to receive said (n+ 1) synchronization pattern at a plurality of inputs corresponding to said inputs in the circuit being tested and to provide a resulting (n+ 1)-level output, the sequence of application of said (n+ 1) synchronization pattern to said reference simulation being such that when a given simulation input signal is being changed from a first to a second of said n logic levels, said one level signal representing the indeterminate logic level is applied to said given input before the second logic level, whereby all of the simulation inputs have an indeterminate level signal applied thereto between the initial pattern increment and the next subsequent pattern increment.

Claim 43

In a method for testing nonlinear circuits having n-level logic comprising applying a changing n-level electrical signal pattern to a plurality of inputs in the circuit being tested, each level being equivalent to one of said logic levels, and synchronously applying said signal pattern respecTively to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of synchronizing the pattern applied to the circuit with the pattern applied to simulation and synchronizing the logic levels in said circuit with the logic levels in said simulation by a method comprising: applying to said plurality of inputs in the circuit being tested, an n-level signal synchronization pattern made up of an initial pattern increment comprising a plurality of signals, each of which is respectively applied to one of said plurality of inputs followed by a next subsequent pattern increment in which each of the signals is at a changed logic level from the coincident signal in the initial pattern; converting the n-level synchronization pattern to an (n+ 1)-level synchronization pattern, in which n levels represent the n levels in the circuit logic and one level represents an indeterminate level in said circuit logic; and applying said (n+ 1) synchronization pattern to a reference simulation of said circuit adapted to receive said (n+ 1) synchronization pattern at a plurality of inputs corresponding to said inputs in the circuit being tested and to provide a resulting (n+ 1)-level output, the sequence of application of said (n+ 1) synchronization pattern to said reference simulation being such that when a given simulation input signal is being changed from a first to a second of said n logic levels, said one level signal representing the indeterminate logic level is applied to said given input before the second logic level, whereby all of the simulation inputs have an indeterminate level signal applied thereto between the initial pattern increment and the next subsequent pattern increment.

Claim 44

The method of claim 34 wherein the (n+ 1)-level synchronization pattern is formed in double-rail logic.

Claim 45

The method of claim 35 wherein a randomly generated n-level electrical signal testing pattern is applied after the synchronization.

Claim 46

In a method for testing nonlinear binary circuits comprising applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of said binary circuit states, and applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of synchronizing the pattern applied to the circuit with the pattern applied to the simulation and synchronizing the logic levels in said circuit with the logic levels in said simulation by a method comprising: applying to said plurality of input points in the circuit being tested, a bilevel signal synchronization pattern made up of an initial pattern increment comprising a plurality of signals, each of which is respectively applied to one of said plurality of input points followed by a next subsequent pattern increment in which each of the signals is at a changed logic level from the coincident signal in the initial pattern; converting the bilevel signal pattern to a three-level signal pattern, in which the first and second levels represent the two levels in the circuit logic and the third level represents an indeterminate binary circuit state; applying said three-level level signal pattern to a reference simulation of said circuit adapted to receive said three-level signal pattern at a plurality of inputs corresponding to said plurality of inputs in the circuit being tested and to provide a resulting three-level output, the sequence of application of said three-level signal pattern to said reference simulation being such that when a given one of said plurality of inputs is being changed from one of said first and second logic levels to the other, said third level is applied to said input being changed before the other changed level is applied, whereby all of the simulation input points have an indeterminate level signal applied thereto between the initial pattern increment and the next subsequent pattern increment.

Claim 47

In a method for testing nonlinear binary circuits comprising applying a bilevel electrical signal pattern to a plurality of input points in the circuit being tested, each level being equivalent to one of said binary circuit states, and applying said signal pattern to a plurality of corresponding inputs in a reference simulation of said circuit, and comparing corresponding resulting outputs from said circuits and said reference simulation, the improvement of synchronizing the pattern applied to the circuit with the pattern applied to the simulation and synchronizing the logic levels in said circuit with the logic levels in said simulation by a method comprising: applying to said plurality of input points in the circuit being tested, a bilevel signal synchronization pattern made up of an initial pattern increment comprising a plurality of signals, each of which is respectively applied to one of said plurality of input points followed by a next subsequent pattern increment in which each of the signals is at a changed logic level from the coincident signal in the initial pattern; converting the bilevel signal pattern to a three-level signal pattern, in which the first and second levels represent the two levels in the circuit logic and the third level represents an indeterminate binary circuit state; applying said three-level level signal pattern to a reference simulation of said circuit adapted to receive said three-level signal pattern at a plurality of inputs corresponding to said plurality of inputs in the circuit being tested and to provide a resulting three-level output, the sequence of application of said three-level signal pattern to said reference simulation being such that when a given one of said plurality of inputs is being changed from one of said first and second logic levels to the other, said third level is applied to said input being changed before the other changed level is applied, whereby all of the simulation input points have an indeterminate level signal applied thereto between the initial pattern increment and the next subsequent pattern increment.

Claim 48

The method of claim 37 wherein the three-level signal pattern is formed in double rail logic.

Claim 49

The method of claim 37 wherein a randomly generated bilevel electrical signal testing pattern is applied after the synchronization.

Claim 50

The method of claim 37 wherein subsequent to synchronization, the testing of the circuit includes: applying a randomly generated bilevel test pattern to said plurality of input points in the circuit being tested; converting said bilevel test pattern to said three-level signal pattern; applying said three level test pattern to said reference simulation at said corresponding plurality of inputs in accordance with the aforementioned sequence of application; and determining whether said third logic level exists in at least a portion of said simulation output after a change in the test pattern is completed, the existence of said third level indicating the change produced race conditions critical to that portion of the output at the third level.

Claim 51

The method of claim 40 including the further steps of converting the simulation output resulting from a three-level test pattern back to the bilevel signal pattern; and inhibiting the comparison of that portion of the simulation output remaining at the third level with the output of the circuit being tested.